Cu contact on NiSi substrate with a Ta/TaN barrier stack

The thermal and electrical stabilities of Cu contact on NiSi substrate with and without a Ta/TaN barrier stack in between were investigated. Four-point probe (FPP), X-ray diffraction (XRD), scanning electron microscopy (SEM), depth-profiling X-ray photoelectron spectroscopy (XPS), and Schottky barrier height (SBH) measurement were carried out to characterize the diffusion barrier properties. The SBH measurement provides a very sensitive method to characterize the diffusion barrier properties for the copper contact on NiSi/Si. The results show that the Ta/TaN stack can be both thermally and electrically stable after annealing at 450 °C for 30 min and it will have a potential application as a diffusion barrier for Cu contact on NiSi.     

Failure mechanisms of PVD Ta and ALD TaN barrier layers for Cu contact applications

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi₂ for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300 mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the α-Ta lattice for PVD barriers between 300 and 500 °C, and induces Ta silicidation at 600 °C. The agglomeration of TaSi₂ seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4 nm thick ALD layers is higher than 500 °C. It is found that the failure of 3 and 4 nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ∼2.2 eV and a pre-exponential factor D₀ of ∼3.8 × 10⁻³ cm²/s.     

NiSi contact metallization using electroless Ni deposition on Pd-activated self-assembled monolayer (SAM) on p-type Si(1 0 0)

In this paper we describe a method to form NiSi contacts using electroless plating of Nickel or Ni alloy on Pd activated self-assembled monolayer (SAM) on p-type Si(1 0 0). Such method allows uniform deposition of very thin, <30 nm, Ni or Ni alloy films. Clean, oxide free, Si substrate was covered with aminopropyltriethoxysilane (APTES) self-assembled monolayer. The surface was activated with Pd-citrate solution followed by electroless plating. The samples were annealed for 1 h in vacuum (∼10⁻⁶ Torr) forming the silicide layer. The annealing temperatures were 400 °C for NiP alloy and 500 °C for NiPW alloy. X-ray diffraction (XRD) measurement confirmed the presence of NiSi phase after annealing. The silicides material properties were characterized using secondary electron microscopy (SEM) analysis, X-ray diffraction (XRD) and X-ray photon spectroscopy (XPS) profiling. The results are reported and summarized.     

A Hafnium interlayer method to improve the thermal stability of NiSi film

The effect of a thin Hafnium interlayer on the thermal stability of NiSi film has been investigated. Both X-ray diffraction and Raman spectra show that no high resistivity NiSi₂ appears in the Hf-additioned films which were post-annealed at temperatures ranging from 600 °C to 800 °C. Auger electron spectroscopy and Rutherford back scattering show that the Hf interlayer has moved to the top of the film after rapid thermal annealing, working as the diffusion barrier for upper Ni atoms. The three-dimensional surface morphology by atom force microscopy shows that the agglomeration of NiSi is effectively suppressed, which is attributed to the barrier effect of the Hf interlayer. The fabricated Ni(Hf)Si/Si Schottky diodes still displays good current-voltage characteristics even after annealed at temperatures varied from 650 °C to 800 °C, which further show that the Hf interlayer can improve the thermal stability of NiSi.     

Boron redistribution during reactive diffusion in Ni-Si contacts

The NiSi silicide that forms by reactive diffusion between Ni and Si-rich active regions of nanotransistors is currently used for contacts in nanoelectronics because of its low resistivity. The redistribution of boron during reactive diffusion between Ni (30 nm) and B doped-Si has been investigated by laser assisted wide-angle tomographic atom probe (LAWATAP). Two states were characterized (room temperature and rapid thermal annealing at 450 °C for 1 min).LAWATAP shows that after deposition of Ni (30 nm) at room temperature a very thin film (7 nm) of Ni silicide was formed. The initial boron distribution in silicon is almost unchanged. After a heat treatment in vacuum at 450 °C (1 min) the nickel monosilicide NiSi was formed. Boron distribution at this stage is very different from that at room temperature. Boron is shown to accumulate at NiSi/Si interface due to snowplow effect. Very small amounts of boron were also found in NiSi phase close to the surface.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

Dopant effects on the thermal stability of FUSI NiSi

The thermal stability of fully silicided (FUSI) NiSi with arsenic or boron doping on silicon on insulator (SOI) was investigated. After the stacks were subjected to a typical back-end of line (BEOL) thermal annealing in a N₂ ambient, abnormal oxidation of As doped FUSI NiSi stacks is observed by X-ray photoelectron spectroscopy (XPS), and confirmed by high-resolution transmission electron microscopy (HRTEM). X-ray diffraction (XRD) results show Ni-rich phases like Ni₃Si are formed due to abnormal oxidation of FUSI NiSi. In contrast to As doped stacks, no phase transformation nor abnormal oxidation are observed for B doped stacks under similar annealing. However, backside secondary ion mass spectrometry (SIMS) results indicate B penetration through a 3 nm SiON layer into the Si channel after N₂ annealing for 4 h at 400 °C. There is no evidence for Ni diffusion into the Si channel for B doped stacks. However, Ni penetration into the Si channel is observed for As doped stacks due to the enhancement of abnormal oxidation of FUSI NiSi.     

超薄Ru/TaN双层薄膜作为无籽晶铜互连扩散阻挡层

研究了钌（Ru) /氮化钽（TaN）双层结构对铜的扩散阻挡特性，在Si (100）衬底上用离子束溅射的方法沉积了超薄Ru/TaN以及Cu/Ru/TaN薄膜，在高纯氮气保护下对样品进行快速热退火，用X射线衍射、四探针以及电流-时间测试等表征手段研究了Ru/TaN双层结构薄膜的热稳定性和对铜的扩散阻挡特性. 同时还对Ru/TaN结构上的铜进行了直接电镀. 实验结果表明Ru/TaN双层结构具有优良的热稳定性和扩散阻挡特性,在无籽晶铜互连工艺中有较好的应用前景.     

Enhancing the reliability of n-p junction diodes using plasma treated tantalum barrier film

The properties of Ta barrier films treated with various plasma nitridations have been investigated by Cu/barrier/Si. An amorphous layer is formed on Ta barrier film after plasma treatments. The thickness of the amorphous layer is about 3 nm. Plasma treated Ta films possess better barrier performance than sputtered Ta and TaN films. It is attributed to the formation of a new amorphous layer on Ta surface after the plasma treatment. Cu/Ta(N,H)/Ta (10 nm)/Si remained stable after annealing at 750 °C. Ta(N,H)/Ta possesses the best thermal stability and excellent electrical properties. Cu/Ta/n⁺-p and Cu/Ta(N,O)/Ta/n⁺-p diodes resulted in large reverse-bias junction leakage current after annealing at 500 °C and 600 °C, respectively. On the other hand, Ta(N,H)/Ta and Ta(N)/Ta diffusion barriers improve the thermal stability of junction diodes to 650 °C. Ta(N,H)/Ta barrier film possesses lowest resistivity among Ta, Ta(N,O)/Ta, and Ta(N)/Ta films. Hydrogen plays an important role in enhancement of barrier properties. It is believed that hydrogen not only induces amorphization on Ta, but also eliminates the oxygen in the film. It is believed that the enhancement of ability against the copper diffusion is due to the combined effects of the hydrogen reaction and nitridation.     

Reliability of multistacked tantalum-based structure as the barrier film in ultralarge-scale integrated metallization

Diffusion barrier properties of Ta films with and without plasma treatments have been investigated in the study. The nitrogen-incorporated Ta films were prepared by NH₃ plasma treatment or reactive sputtering. Barrier properties were evaluated by sheet resistance, X-ray diffraction, transmission electron microscopy, X-ray photoelectron spectroscopy and reverse-biased junction leakage current. An amorphous-like TaN_x layer was formed on Ta barrier film after plasma treatments. The thickness of the amorphous TaN_x layer is about 3 nm and NH₃ plasma-treated Ta films (TaN_x/Ta) possess lower resistivity and smaller grain sizes. The Cu/TaN_x/Ta(10 nm)/Si remained stable after annealing at 750 °C for 1 h. NH₃ plasma-treated Ta films (TaN_x/Ta) possess better thermal stability than Ta and TaN films. It is attributed to the formation of a new amorphous layer on the surface of Ta film after the plasma treatments. For thermal stability of Cu/Ta(-N)/n⁺-p diodes, Cu/Ta/n⁺-p and Cu/TaN/n⁺-p junction diodes resulted in large reverse-bias junction leakage current after annealing at 500 and 525 °C, respectively. On the other hand, TaN_x/Ta diffusion barriers will improve the integrity of Cu/Ta(-N)/n⁺-p junction diodes to 650 °C.     

Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi

It is reported that the thermal stability of NiSi is improved by employing respectively the addition of a thin interlayer metal (W, Pt, Mo, Zr) within the nickel film. The results show that after rapid thermal annealing (RTA) at temperatures ranging from 650 °C to 800 °C, the sheet resistance of formed ternary silicide Ni(M)Si was less than 3 Ω/□, and its value is also lower than that of pure nickel monosilicide. X-ray diffraction (XRD) and raman spectra results both reveal that only the Ni(M)Si phase exists in these samples, but the high resistance NiSi₂ phase does not. Fabricated Ni(M)Si/Si Schottky barrier devices displayed good I-V electrical characteristics, with the barrier height being located generally between 0.65 eV and 0.71 eV, and the reverse breakdown voltage exceeding to 40 V. It shows that four kinds of Ni(M)Si film can be considered as the satisfactory local connection and contact material.     

Investigations of thermal annealing effects on electrical and structural properties of SrTaO based MIM capacitor

The annealing effects on dielectric and electrode materials in Ti/SrTaO/TaN/TiN/Ti/Si metal-insulator-metal (MIM) capacitors were studied. The electrical and structural properties were investigated after subjecting the samples to annealing temperatures of 500 °C, 700 °C and 900 °C. The electrical results revealed that the dielectric constant (k value) of Sr-Ta-O increased from 18 to 50 with increasing annealing temperature. This improvement in k value can be associated to the crystallization of dielectric layer. However, the leakage current density increased several orders of magnitudes with increase of the annealing temperatures. This observation was attributed to crystallization of dielectric, degradation of TaN electrode and out-diffusion of Si from the substrate.     

A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300 mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10 nm reacts with Si substrate and forms TaSi₂ at 650 °C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90 nm contacts. Top-view SEM observation on the samples after 420 °C sintering demonstrates that the Cu diffusion barrier is effective. I_on-I_off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi₂/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.     

Comparison of PVD, PECVD & PEALD Ru(-C) films as Cu diffusion barriers by means of bias temperature stress measurements

The diffusion barrier properties of PVD Ru and PECVD / PEALD Ru-C films, deposited by RuEtcp₂ precursor and N₂/H₂ plasma, were compared on the basis of bias temperature stress measurements. An MIS test structure was used to distinguish between thermal diffusion induced by annealing and a Cu field drift due to applied electric fields. BTS-CV, TZDB and TDDB measurements revealed that the barrier performance is significantly better for PEALD and PECVD Ru-C films. This improvement is associated with carbon impurities in the Ru films with a concentration in the order of several percent according to ToF-SIMS and ERDA. The TDDB mean time to failure at 250 °C, +5 MV/cm was 7 s for PVD Ru samples, ≈500 s for PECVD Ru-C, ≈800 s for PEALD Ru-C and >3600 s for PVD TaN. Triangular voltage sweep measurements at 300 °C, 0.1 V/s confirmed the presence of Cu ions inside the SiO₂ for degraded dots, in contrast to the Al reference sample and to PVD TaN, which performed best among all the Cu barriers under test. XRD data suggests that PEALD and PECVD Ru-C films are only weakly crystalline.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

Texture of atomic layer deposited ruthenium

Ruthenium films were grown by plasma enhanced atomic layer deposition (ALD) on Si(1 0 0) and ALD TiN. X-ray diffraction (XRD) showed that the as-deposited films on Si(1 0 0) were polycrystalline, on TiN they were (0 0 2) oriented. After annealing at 800 °C for 60 s, all Ru films were strongly (0 0 2) textured and very smooth. Electron backscatter diffraction (EBSD) and transmission electron microscopy (TEM) demonstrated that the lateral grain size of the annealed films was several 100 nm, which was large compared to the 10 nm thickness of the films. No ruthenium silicide was formed by annealing the ALD Ru films on Si(1 0 0). Comparison with sputter deposited films learned that this occurred because the ammonia plasma created a SiO_xN_y reaction barrier layer prior to film growth.     

Barrier layer thickness analysis for reliable copper plug process in CMOS technology

Copper (Cu) replacing conventional tungsten (W) based 1st contact plug has become necessary for high performance CMOS. For a reliable and well optimized Cu plug, process selection and integration of plug diffusion barrier is an important task. In this work, we investigate barriers for Cu plug technology for CMOS process. Single layer TaN and bi-layer Ta + TaN barrier materials were studied for their effectiveness in preventing Cu diffusion into device active regions for backend thermal stress conditions. The degradation of device characteristics was used as monitor of robustness of barrier reliability. Diffusion of Cu in multilayer plug structure is modeled to explain observed stress behavior. From the model studies, the critical barrier layer thickness needed to prevent Cu diffusion is determined. We show than that a ∼7 nm sidewall barrier is effective in preventing Cu diffusion into Si at up to 350 °C/60 min only, while a minimum thickness of ∼10 nm is needed for blocking copper diffusion at 420 °C/30 min. Using multilayer Cu diffusion model, an optimized process window for reliable, low contact resistance Cu plug technology for CMOS process can be obtained.     

Improving the electrical integrity of Cu-CoSi/sub 2/ contacted n/sup +/p junction diodes using nitrogen-incorporated Ta films as a diffusion barrier

The study on improving the electrical integrity of Cu-CoSi/sub 2/ contacted-junction diodes by using the reactively sputtered TaN/sub x/ as a diffusion barrier is presented in this paper. In this study, the Cu (300 nm)-CoSi/sub 2/ (50 nm)/n/sup +/p junction diodes were intact with respect to metallurgical reaction up to a 350/spl deg/C thermal annealing while the electrical characteristics started to degrade after annealing at 300/spl deg/C in N/sub 2/ ambient for 30 min. With the addition of a 50-nm-thick TaN/sub x/ diffusion barrier between Cu and CoSi/sub 2/, the junction diodes were able to sustain annealing up to 600/spl deg/C without losing the basic integrity of the device characteristics, and no metallurgical reaction could be observed even after a 750/spl deg/C annealing in a furnace. In addition, the structure of TaN/sub x/ layers deposited on CoSi/sub 2/ at various nitrogen flow rates has been investigated. The TaN/sub x/ film with small grain sizes deposited at nitrogen flow ratios exceeding 10% shows better barrier capability against Cu diffusion than the others.     

Characteristics of thin lanthanum lutetium oxide high-k dielectrics

In this work, we evaluate the thermal stability of thin film lanthanum lutetium oxide (LLO) on silicon deposited using molecular beam epitaxy (MBE). Thin LLO films are capped with TaN and annealed at 700 °C or 900 °C in nitrogen or oxygen ambients. SIMS analysis indicates no La and Lu up diffusion into TaN after annealing. However, after a 900 °C anneal Si is detected in the LLO. SIMS data also suggested growth of interfacial oxide upon anneal. Cross sectional TEM of as deposited films show a sharp high-k/Si-substrate interface with very thin interfacial layer. An increase in the LLO layer thickness, and the interfacial layer thickness between the LLO and the Si-substrate is observed after annealing. Capacitors with LLO dielectrics were also formed using TiN electrode and low leakage is demonstrated for samples annealed at 700 °C. However, a large positive flatband voltage shift and an increase in leakage is observed in LLO capacitors after undergoing 900 °C anneal with a TiN metal gate.     

Study of Ni/Si(1 0 0) solid-state reaction with Y addition

The characteristics of Ni/Si(1 0 0) solid-state reaction with yttrium (Y) addition are studied in this paper. Film stacks of Ti(20 nm)/TiN(40 nm)/Ni(8 nm)/Y(4 nm)/Ni(8 nm)/Si(1 0 0) and Ti(20 nm)/TiN(40 nm)/Ni(7 nm)/Y(6 nm)/Ni(7 nm)/Si(1 0 0) were prepared by physical vapor deposition. After solid-state reaction between metal films and Si was performed by rapid thermal annealing, various material analyses show that NiSi forms even with the addition of Y, and Ni silicidation is accompanied with Y diffusion in Ni film toward its top surface. The electrical characteristic measurements reveal that no significant Schottky barrier height modulation with the addition of Y occurs.