Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.     

Dry etching process for bulk finFET manufacturing

This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125 nm height which is used as a fin and a sloped bottom of 200 nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional α-C hard mask of 90 nm (with antireflective SiOC coating of 35 nm) on top of the STI stack (70 nm nitride on top of 8 nm oxide). The nitride layer and the top straight part of the fin is patterned using CH₂F₂/SF₆/N₂ chemistry and α-C as a mask, while the bottom sloped part is patterned using Cl₂/O₂/N₂ chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged.     

Carbon etching with a high density plasma etcher

Generating suitable passivation on the carbon sidewall is a major challenge facing carbon etching especially for films thicker than 500 nm. Patterning carbon hard mask stacks for sub 90 nm technologies was tested for three different O₂-based chemistries using an inductively coupled plasma etch tool. The results show that the etched carbon profiles are highly dependant upon the O₂ flow and the total time of the etch process. Extended over etch times quite often initiates lateral etching and rapid loss of profile and critical dimension. An HBr/O₂/N₂ chemistry has been shown to provide the best options for profile control and more resistance to profile loss during extended over etching than the other chemistries which were tested during this study.     

Patterning of narrow porous SiOCH trenches using a TiN hard mask

For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO₂ hard mask may lead to severe profile distortions, attributed to TiF_x compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.     

A robust spacer gate process for deca-nanometer high-frequency MOSFETs

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 μm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 μS/μm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 μA/μm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.     

Influence of MEEF change on the mask shadowing effect in extreme ultraviolet lithography

The influence of mask error enhancement factor (MEEF) on the mask shadowing effect was investigated for extreme ultraviolet lithography. Imaging properties including horizontal-vertical (H-V) CD (critical dimension) bias and MEEF change through the pitch according to absorber thickness and process condition were studied using aerial image simulation. The mask structure used in this study consisted of tantalum nitride (TaN) absorber and 2 nm ruthenium (Ru) capping layer on the 40 pair of Mo-Si multilayer. As the absorber thickness increased and the pattern pitch decreased, both H-V CD bias and MEEF increased. At the illumination condition of 0.32 numerical aperture (NA), the H-V CD bias variation through the pitch was negligible and slightly increased at 1:1 pitch, while it steeply increased at 1:1.2 and 1:1 pitch for NA of 0.25. The MEEF value was below 1.5 for all calculated absorber thicknesses when the pitch was from 1:1.2 to 1:5, whereas it was 3 with 64 nm thick TaN for 1:1 pitch at vertical pattern. With the increment of absorber thickness, the MEEF difference between the horizontal and vertical pattern increased. We also calculated the H-V overlapping process window (PW) according to TaN thickness using 22 nm 1:1 line and space (L/S) pattern. As absorber thickness decreased, the overlapping zone in the EL of the focus-exposure plots between the horizontal and vertical features increased. Enough image contrast and H-V overlapping PW could be achieved by applying 38 nm thick TaN.     

The etchback approach: Enlarged process window for MuGFET gate etching

We present a new method to enlarge the process window for gate patterning on a surface with high topography. We have compared two approaches for the patterning of a poly-Si gate with oxide hard mask (HM) as used in multi-gate field effect transistors. In the first approach, referred to as ‘direct deposition’, a poly-Si layer of 60 nm is deposited on the substrate, whereas in the second, and new approach 200 nm poly-Si is deposited and anisotropically etched back to 60 nm. All subsequent process steps (i.e. HM deposition, lithography and gate etch) are identical. From ellipsometric thickness measurements, we conclude that for the etchback case the poly-Si film has a larger within-wafer-non-uniformity due to the deposition of a thicker film. On the other hand, top down and cross-section SEM after gate etch show that for the etchback approach there is a larger process window with respect to avoiding micro-masking by the oxide HM at topography steps. We demonstrate that less over-etch is needed during the HM opening step to achieve residue free patterning of the poly-Si film. For a poly-Si thickness of 100 nm, we were able to obtain a residue free gate etch process for both the direct deposition and the etchback approach. Electrical evaluation shows that device performance is not compromised when using the etchback approach.     

Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell

FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32 nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22 nm node 6T-SRAM cell. Key in this work was achieving the required CD and profile target specs for the fin and the gate level. Also, the implant levels, though still a 450 nm pitch, turned out to be more difficult than expected because of the underlying topography. All this work resulted in the first electrically functional 22 nm node SRAM cell, with the contact and metal level exposed on the ASML EUV α-demo tool.     

Potential applications of negative tone development in advanced lithography

Advanced lithography requires resolution enhancement techniques (customized illumination mode, litho friendly design), and alternative process flow schemes (double exposure, double patterning) in order to meet the requirements of the ITRS technology roadmap and to extend the applications of a full-field scanner with a 1.35 numerical aperture (NA) that represents the physical limit of water-based immersion ArF lithography.Today, one of the most interesting alternative processes uses the patterning inversion through a negative tone development (NTD) process step. Traditionally, the patterning (contacts or trenches) is done by using a dark field mask in combination with positive tone resist and positive tone development (PTD). By using a solvent-based developer (NTD) and a bright field mask, the same features can be transferred into a positive resist with the benefit of better image contrast and, consequently, better line width roughness (LWR) and resolution.In this work we have explored the potential applications of NTD for trenches and contact holes for the 45 nm technology node requirements and beyond. The NTD process is a promising option considering the impact on process window, LWR, CD uniformity and defectivity. The experimental result of this alternative approach to print critical dark field levels in an advanced lithography boundary has been explored.     

Fabrication of nickel stamp with improved sidewall roughness for optical devices

We proposed the simple and attractive fabrication method of nickel stamp with improved sidewall roughness for polymeric optical devices. For this, the imprinted optical devices patterns under optimum imprinting conditions were annealed to improve the sidewall roughness generated by the DRIE process in the silicon stamp fabrication. The annealed sidewall roughness is reduced to 24.6 nm, nearly decreasing by 76% compared with the result before the annealing. Then, low cost and durable nickel stamp with improved sidewall roughness was fabricated by the annealed polymeric patterns being used as original master for electroforming process. And, we verified the superiority of the improved nickel stamp by comparing the optical propagation losses for optical waveguides to be fabricated, respectively, using the nickel stamp and original silicon stamp. The optical waveguides fabricated by the imprint lithography using the improved nickel stamp was demonstrated that their optical losses were reduced as 0.21 dB/cm, which was less than the propagation loss for polymeric waveguides using the conventional original silicon stamp. This result could show the effectiveness of the fabricated nickel stamp with improved sidewall roughness. Furthermore, we were able to successfully fabricate a polymeric 1 × 8 beam splitter device using the improved nickel stamp. And, the insertion loss for eight channels obtained to be from 10.02 dB to 10.91 dB.     

Improved sidewall morphology on dry-etched SiO2 masked GaN features

A number of different methods have been investigated for minimizing sidewall roughness on dry etched GaN features formed using high density plasmas. In many instances, striations on dry etched mesas are a result of roughness in the initial photoresist mask employed, and this roughness is transferred sequentially to the dielectric mask and then to the GaN. Flood exposure of the photoresist, optimization of the bake temperature, choice of plasma chemistry, and ion flux/energy for patterning the dielectric mask all influence the final GaN sidewall morphology.     

Electron beam nanolithography in AZnLOF 2020

We present a lithography process using electron beam lithography with an optical resist AZnLOF 2020 for pattern transfer. High-resolution 100 keV electron beam lithography in 400 nm layers of negative resist AZnLOF 2020 diluted 10:4 with PMGEA is realized. After the electron beam lithography process, the resist is used as a mask for reactive ion etching. We performed the transfer of patterns by RIE etching of the substrate allowing a final resolution of 100 nm. We demonstrate the patterning in an insulating layer, thus simplifying the fabrication process of various multilayer devices; proximity correction has been applied to improve pattern quality and also to obtain lines width according to their spacing. This negative resist is removed by wet etching or dry etching, could allow combining pattern for smallest size down to 100 nm by EBL techniques and for larger sizes by traditional lithography using photomask.     

Carbon hard masks for etching sub-90 nm structures

Carbon hard mask structures have been used to etch a variety of materials typically used in sub 90 nm DRAM manufacture. The results indicate that carbon hard masks can be used very effectively to structure oxide, nitride and metal films giving the CD performance required for the technologies being investigated.     

Simulation and verification of void transfer patterning (VTP) technique for nm-scale features

This paper investigates simulation of a patterning technique for defining sub-lithographic features. The technique studied involves intentional creation of voids using a conformal chemical vapor deposition (CVD) followed by controlled etch-back to form nanoscale pores. This method provides features that are independent of lithographically defined parent holes and exhibit lower critical dimension (CD) variations. It offers efficient low thermal budget and backend process compatible integration scheme that requires just one additional mask level. The void diameter obtained in this work is 74 nm i.e. ∼10× reduction from lithographically defined hole of 714 nm using i-line lithography. Critical parameters affecting the void formation and the final pore size have been identified and modeled. Simulation of the void transfer process has been investigated using plasma etch module of ‘Elite’ by Silvaco that employs 2-D Monte Carlo ion transport modeling. The results of this investigation show that the geometrical design parameters can be coupled with the plasma process simulations to develop an efficient module for the void transfer process.     

Soft UV-NIL at 20 nm scale using flexible bi-layer stamp casted on HSQ master mold

In this paper we present a comparative study of two e-Beam Lithography (EBL) processes for Nanoimprinting Lithography (NIL) master mold, i.e. the standard PMMA based EBL Si patterning process and the HSQ process. 20 nm features with minimal sidewall roughness and high uniformity are demonstrated on large surface by using HSQ process. Moreover, to validate this ultra-high resolution HSQ EBL process and to check NIL resolution performances, soft UV-NIL replications were performed using soft hard-PDMS/PDMS bi-layer stamps casted on the HSQ master mold. We demonstrate the replication of sub-20 nm nanodots of high density (pitch 60 nm) with a good uniformity on the whole field area.     

Investigation of high-performance sub-50 nm junctionless nanowire transistors

The performances of the junctionless nanowire transistor (JNT) are evaluated under high-performance (HP) ITRS device technical requirements for the 25 nm technology node. The electrical characteristics of the devices are obtained from numerical simulations. The threshold voltage of JNT can be easily adjusted by changing different variable parameters such as fin width, fin thickness, doping concentration, gate oxide thickness and gate work function. The variation of threshold voltage with physical parameters is analyzed. The current drive is controlled by doping concentration and nanowire size. For gate length down to 25 nm, a 30-40% increase in drain current is also reported by using a fin aspect ratio of 2 instead of 1. Additional source and drain implantation can be applied to improve the current drive.     

Simple technique to fabricate microscale and nanoscale silicon waveguide devices

Fabrication of microscale and nanoscale sili-con waveguide devices requires patterning silicon, but until recently, exploitation of the technology has been restricted by the difficulty of forming ever-small features with minimum linewidth fluctuation.A technique was developed for fabricating such devices achieving vertical sidewall profile, smooth sidewall roughness of less than 10 nm, and fine features of 40 nm.Subsequently, silicon microring resonator and silicon-grating coupler were realized using this technique.     

Platinum chemical mechanical polishing (CMP) characteristics for high density ferroelectric memory applications

The key component of ferroelectric random access memory (FeRAM) is a capacitor including a ferroelectric thin film and electrode materials. Platinum is one of the suitable metals which meet requirements such as low resistivity, high thermal stability, and good oxygen resistance. Generally, the ferroelectric and the electrode materials were patterned by a plasma etching process. The application possibility of chemical mechanical polishing (CMP) processes to the patterning of ferroelectric thin film instead of plasma etching was investigated in our previous study for improvement of an angled sidewall which prevents the densification of FeRAM. In this study, the characteristics of platinum CMP for FeRAM applications were also investigated by an approach as bottom electrode materials of ferroelectric material in CMP patterning. The removal rate was increased from 24.81 nm/min by the only alumina slurry (0.0 wt% of H₂O₂ oxidizer) to 113.59 nm/min at 10.0 wt% of H₂O₂ oxidizer. Electrochemical study of platinum and alumina slurry with various concentrations of H₂O₂ was performed in order to investigate the change of the removal rate. The decreased particle size in the alumina slurry with an addition of 10.0 wt% H₂O₂ oxidizer made the improved surface roughness of the platinum thin films. Micro-scratches were observed in all polished samples.     

Reliability of copper low-k interconnects

For the implementation of copper and low-k materials into a tight pitch damascene interconnect architecture it is important to understand and correctly describe the underlying degradation mechanisms during reliability testing. Based on the understanding solutions can be proposed for avoiding fast degradation. While the physical understanding of electromigration mechanisms is less of a debate, technological challenges towards the fabrication of metal wires/vias able to carry the ever increasing current densities are enormous. Recently a number of novel metallization schemes including ruthenium and its alloys or self-forming barriers were proposed. As a consequence, some of the thermodynamic and kinetic behavior of the system can be modified when compared to the conventional Ta-based metallization. Another important component of the system is the insulating low-k dielectric. When scaling the critical dimensions into 50 nm ½ pitch and beyond, the impact of layout and line edge roughness becomes important. If a double patterning approach is used for printing a tight metal pitch, then misalignment between the different photos will exacerbate the layout induced effects. The choice of dielectric material, test structure design and damascene process steps will contribute on top of these effects. Based on recent understanding we review some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint.     

Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices

In this work, we investigate the gate voltage and the geometry dependence of the series resistance and the carrier mobility in n-type and p-type FinFETs. A significant gate voltage dependence of the series resistance is observed, which is ascribed to the conduction modulation of the LDD region under the gate. The fin width dependence of the series resistance is investigated and two simple methods of normalization are compared. Mobility data in narrow (W_fin = 30 nm) and wide fin (W_fin = 3μm) have been compared. N-FinFETs show a higher mobility compared to the p-FinFET in both cases, but for narrow fins the difference is reduced since the mobility on the sidewalls improves for holes but degrades for electrons. We show that without taking into account the gate voltage dependence of the series resistance the mobility is significantly underestimated.