A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion

This paper presents a novel linearized transconductor architecture working at 1.25 V in a 0.8-/spl mu/m CMOS technology with very low power consumption. The special features of the floating-gate MOS (FGMOS) transistor are combined in weak and strong inversion leading to a simplified topology with fewer stacked transistors and a very low noise floor. The design methodology is thoroughly explained, together with the advantages and disadvantages of working with the FGMOS transistor. Furthermore, second-order effects arising from nonideal behavior of the device are analyzed and limits for the performance are established. Experimental results from a second-order low-pass/bandpass filter that was implemented using the transconductor show a tunability of over one and a half decades in the audio range, a dynamic range of over 62 dB, and a maximum power consumption of 2.5 /spl mu/W. These results demonstrate the suitability of the FGMOS transistor for implementing analog continuous-time filters, while at the same time pushing down the voltage limits of process technologies and simplifying the circuit topologies to obtain significant power savings.     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

Low-power analogue computational blocks based on high-performance floating-gate MOSFET resistor

This article proposes a new FGMOS-based programmable FGMOS resistor. A highly linear resistor is implemented by cancelling the non-term present in the drain current equation of MOSFET operating in the linear region. The inherited features of FGMOS resistor are simplicity, programmability, wider bandwidth and very low power dissipation without supply voltage. The power dissipation of the proposed FGMOS resistor is only 985 nW. Analogue computational blocks such as programmable reciprocal circuit, current to voltage converter and low-pass filter as applications of proposed programmable FGMOS resistor are also suggested. The power dissipation of reciprocal circuit and low-pass filter are 14.7 and 131 µW, respectively. To demonstrate the efficacy of the circuits, simulations are carried out using SPICE on 0.13 µm CMOS technology.     

A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and ?3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

A very compact, 0.4 V DTMOS CCII employed in an audio-frequency filter

This paper presents an ultra low-voltage, ultra low-power, very compact, dynamic threshold voltage MOS transistor (DTMOS)-based CCII circuit. The proposed circuit is capable of operating under ± 0.2 V symmetric supply voltages. The circuit topology is very compact and consists of only four DTMOS transistors and four ordinary NMOS transistors. The total power consumption of the circuit is found as only 214 nW while all transistors are working in the subthreshold region. The current conveyor has 570 kHz 3 dB-bandwidth from X to Y terminal for the voltage gain and has low, 0.2 % following error between these terminals for inputs not exceeding ± 60 mV. TSMC 0.18 µm process technology parameters are used in the design of the proposed CCII block which is then employed in an audio-frequency, second-order, band-pass filter configuration where real speech signals are fed to the input of the filter to further investigate its characteristics. Close agreement is found between theoretical study and simulated responses.     

Low-voltage linear transconductor and a memory current using the MIFGMOS Transistor

The aim of this article is to probe the advantages that the Multi-Input Floating Gate MOS (MIFGMOS) transistor has versus the conventional MOSFET transistor in order to design analogue circuits with low-voltage operation and good linearity. To show this, the design and implementation of both a voltage to current converter (VIC) cell and a memory current cell (MIC) using MIFGMOS transistors is presented. The development is based on mathematical and simulation analysis as well as experimental results. Both cells present good performance and linearity according to theoretical analysis with a supply voltage of 1.7 V and a power consumption of about 20 μW, despite the long channel technology. These characteristics could be very important in analogue and mixed signal applications requiring low supply voltage and low power consumption. The cells presented here can be part of a sample and hold circuit operating in current mode, but applications are not restricted. Additionally, a comparison between simulation and experimental results obtained when we tested five 3-input MIFGMOS transistors are included to show their properties and behavior.     

Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors

In this paper, we present voltage-mode and current-mode computational circuits using floating-gate MOS (FGMOS) transistors, operating in saturation region. The circuits are designed using two FGMOS basic-cells, each one formed by three floating-gate transistors with common source. The first basic cell is connected in voltage mode, while the second one is connected in current-mode configuration in order to implement voltage and current-mode circuits, respectively. Using the basic FGMOS cells, voltage and current squarers, four-quadrant multipliers and a current square rooter are designed. Mismatches and distortion analysis for the proposed circuits have been elaborated. The most important advantages are, rail-to-rail dynamic input range, low distortion and ability for either differential or single-ended input signals. Simulation results demonstrate the feasibility and the accuracy of the circuits.     

A low voltage 8-bit digital-to-analog converter using floating gate MOSFETs

A new low voltage digital-to-analog conversion (DAC) architecture is proposed using weighted summation of voltages at the input terminals of a Floating Gate MOSFET (FGMOS). An 8-bit DAC has been designed based on this architecture and its simulation results are provided to verify its operation at ±1.0 V. The circuit possesses good accuracy, fast dynamic performance and low power consumption. The circuit operation was verified through SPICE simulations carried out using 0.13 μm CMOS technology.     

A low power sub-BGR with multi-curvature self-compensation

This paper proposes a low power sub bandgap reference (sub-BGR) with a novel multi-curvature self-compensation. The proposed circuit generates a curvature-compensation-less reference voltage (V_{REF_NC}), which is compared with the emitter–base voltage of a PNP transistor to generate a pair of complementary curvature currents. The curvature currents are used to compensate the temperature coefficient (TC) of the voltage V_{REF_NC} itself, resulting in a low-power and low-TC sub-BGR. The proposed circuit is implemented in a standard 65 nm complementary metal oxide semiconductor process. Simulation and measured results show the total power consumption is about 230 nW at the minimum supply voltage of 1.0 V. The power supply rejection ratio at low frequency is less than ?66 dB. After trimming, the average TC of 23 ppm/°C in the temperature range of ?45 to 125 °C and the accuracy of ± 0.15% (σ/µ) can be achieved.     

Designer's Casebook-current-mode minimax circuit

The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and the gate-source voltage, transistor pairs may operate in strong, moderate and weak inversion. Therefore, the circuit can also be implemented in bipolar as well as MOS technology. The circuit has many useful applications in modern signal processing     

Over rail-to-rail fully differential voltage-to-current converters for nm scale CMOS technology

The converters presented in this paper are based on long channel complementary MOS transistors, instead of the commonly used differential amplifiers or differential transistor pairs which are difficult to implement in low voltage, nm scale CMOS technology. Nonlinearities of drain currents can be cancelled in the fully differential structure. As a result, the low power, nanometre standard digital CMOS technology converters are obtained. Layout examples are designed in 65 nm TSMC technology. Post-layout simulations show that the range of input voltage over rail-to-rail is achieved with very good linearity and reduced harmonic distortion.     

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 μm process parameters. The ac simulation results of amplifier show that GBW is 9 MHz and power consumption is 0.5 mW.     

Modeling of the MOSFET inversion charge and drain current, inmoderate inversion

The widespread use of MOS technology in analog circuit design demands a precise and efficient circuit simulation model of the MOS transistor valid in all regions of inversion. Currently available circuit simulation models fail in the intermediate range of gate voltages, known as the moderate inversion region. Expressions characterizing the large-signal behavior of the long-channel MOS transistor in the moderate inversion region are derived. The correct dependencies on all the physical and process parameters are preserved by a careful approximation to the physical equations, based on the charge sheet assumption. Another goal is to develop expressions that treat the moderate inversion as a small, voltage-dependent correction to currently existing simplified models. This approach should allow a simple modification of the existing circuit simulation models to improve the accuracy in moderate inversion. The model was compared with a numerical charge sheet model and with experimental measurements of a long-channel, ion-implanted NMOS transistor. The expressions could serve as a basis for a comprehensive MOSFET circuit simulation model     

Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.     

Low voltage and low frequency current mirror using a two-MOSsubthreshold op amp

The authors describe a novel current mirror for low voltage and low frequency application, which uses an op amp with only two MOS transistors operating in the weak inversion region. The advantages of the circuit are low voltage operation, small chip area, high output resistance and no bias current (voltage). The proposed circuit is confirmed by SPICE simulation     

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

The MOS inversion layer as a minority carrier injector

In this paper we report the first experimental demonstration of the concept of MOS inversion layer injection (ILI). The new physical concept is based on the use of a MOS inversion layer as a minority carrier injector as part of a dynamic junction. The carrier injection of such a junction is entirely controlled by the MOS gate. Moreover, when the gate potential is reduced under the MOS threshold voltage, the junction collapses ensuring a very efficient turn-off mechanism. Based on this concept we propose two novel lateral three-terminal structures termed inversion layer diode (ILD) and inversion layer bipolar transistor (ILBT). The concept of inversion layer injection can be applied in power devices where effective MOS gate control of the active junctions is important     

Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

A novel multiple-selected and multiple-valued memory (MSMVM) design using the negative differential resistance (NDR) circuits is demonstrated. The NDR circuits are made of Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). During suitably designing the parameters and connecting three MOS–HBT–NDR circuits, we can obtain the three-peak current–voltage (I–V) curves with different peak currents in the combined I–V characteristics. For the traditional resonant-tunneling-diode (RTD) memory circuit, one can only obtain four-valued memory states using a constant current source to bias the three-peak NDR circuit. However in this paper, we utilize two switch-controlled current sources to bias the three-peak NDR circuit at different current levels. By controlling the switches on and off alternatively, we can obtain the four-valued, three-valued, two-valued, and one-valued memory levels under the four different conditions. Our design is based on the standard 0.35 μm SiGe BiCMOS process.     

采用神经MOS晶体管的低压四象限模拟乘法器的设计

神经 MOS晶体管是最近几年才发明出来的一种高功能度的器件。本文以新开发的神经MOS晶体管的 SPICE宏模型为模拟和验证的工具 ,讨论了采用这种器件实现低压四象限模拟乘法器的系统化设计思想和方法。基于这种设计思想和方法 ,设计了一种大输入范围的低压(± 1 .5V)四象限模拟乘法器电路 ,给出的模拟结果验证了理论分析。