High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

Superbeta polysilicon emitter transistors

In-situ phosphorus-doped polysilicon emitters deposited on monocrystalline silicon substrates at a temperature of 627°C and subjected to no additional high-temperature annealing are shown to be capable of giving Gummel numbers GEin excess of 10¹⁵scm^-4. Polysilicon emitters formed in this way have been used to produce superbeta transistors with performance comparable to the record levels recently reported for MIS emitter devices. In particular, common-emitter current gains β in excess of 30000 have been obtained at low VCBvalues.     

Current gain in polysilicon emitter transistors

The common-emitter current gain β in a shallow polysilicon emitter transistor is derived by solving the minority-carrier transport equation in the silicon-polysilicon structure. Coupled With the majority-carrier transport, an equation for the current gain is obtained which depends on the physical properties of the polysilicon as well as the silicon emitter and base doping profiles. The calculations are based on the carrier trapping model proposed in the literature and ignore any minority-carrier recombinations. The model predicts the current gain of a polysilicon emitter transistor increases at low current and high temperature and approaches that of a conventional metal contact transistor at high current and low temperature. This is due to the potential barrier across the grain boundaries, while impeding the majority-carrier flow, inject minority carriers as a bias is developed across the grain boundaries. It also predicts a decrease in cutoff frequency fTdue to minority carriers stored in the polysilicon.     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

On the modeling of polysilicon emitter bipolar transistors

In this paper, an attempt is made to derive a general analytical formulation for the current gain and emitter transit time of a polysilicon emitter bipolar transistor (BJT), which includes all previous models as particular cases. Firstly, it is shown that the minority-carrier injection and storage in the polysilicon region can be simply described by effective values of the minority-carrier diffusion length and mobility. These quantities are precisely defined, and depend on the microscopic transport properties of polysilicon grains and grain boundaries. Secondly, a general expression for the effective recombination velocity relative to the poly/mono interface is derived, which includes, and in some cases extends, all previous approaches. This results in a simple and general formulation which avoids some unnecessary simplification present in nearly all previous treatments, and allows easy comparison of the different models for the poly/mono interface and a clear assessment of the relevance of each physical mechanism. Finally, minority-carrier injection and storage in the single-crystal region is addressed. The effect of oxide breakup on both current gain and emitter transit time is also considered, and different models are compared     

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.<>     

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

Measurements of emitter resistance have been made on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors, fabricated with or without an interfacial oxide layer. It is found that the emitter resistance of phosphorus-doped transistors is considerably lower than that of arsenic-doped transistors. In addition the presence of a deliberately grown interfacial oxide layer leads to a significant increase in emitter resistance for both arsenic- and phosphorus-doped devices.     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

Heterojunction tunnelling model for pnp and npn polysilicon emitter bipolar transistors

A new tunnelling model is described which treats the interfacial layer in a polysilicon emitter transistor as a wide bandgap semiconductor. Potential barriers are formed in the valence and conduction bands, the sizes of which vary with the dopant type and concentration in the interfacial layer.<>     

Impact of fluorine incorporation in the polysilicon emitter of NPNbipolar transistors

We demonstrate that fluorine incorporation in the polysilicon emitter of NPN bipolar transistors significantly reduces the current gain h_fe. The gain degradation can be related to a reduction of the barrier to hole transport at the poly-Si/mono-Si interface. In addition to a gain reduction, fluorinated-emitter transistors display lower base recombination currents (at low base-emitter biases) than nonfluorinated emitter devices, suggesting that fluorine passivates recombination centers in the emitter-base space charge region     

Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications

This paper is a thorough overview on polysilicon bipolar junction transistors’ (BJTs) reliability, with focus on transistors for digital applications, where the base–emitter junction switches from forward to reverse bias (low fields) and the base–collector junction is reverse biased at high fields. The effects of base–emitter reverse biasing are generation, charging and discharging of traps in silicon oxide or at the Si–SiO₂ interface near the base–emitter junction; their understanding is essential to model transistor current gain degradation and low frequency noise increase. Failure modes and mechanisms, degradation kinetics, lifetime models and physical phenomena related to device aging will be discussed. The base–emitter junction is also stressed by high currents, which lead, for example, to electromigration phenomena. The base–collector junction degradation is mainly due to high field and impact-ionization effects. Reliability constraints are now an important component of a correct design methodology in deep-sub-micron integrated circuits.     

Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors

Two types of polysilicon emitter transistors have been fabricated using identical processing except for the surface treatment prior to polysilicon deposition. The first type was given a dip etch in buffered hydrofluoric acid, which was intended to remove any interfacial oxide, while the second type was given an RCA clean, which was intended to grow an interfacial oxide of known thickness. Detailed electrical measurements have been made on these devices including the temperature dependence of the gain over a wide temperature range. The transistors given an RCA clean have gains approximately five times higher than those given an HF etch. In addition, the temperature dependence of the gain is different for the two types, with the HF devices exhibiting a much stronger dependence at high temperatures than the RCA devices. A detailed comparison is made with the theory and it is shown that the characteristics of the HF devices can largely be explained using a transport theory, while those of the RCA devices can be fully explained using a modified tunneling theory.     

Analysis of emitter efficiency enhancement induced by residualstress for in situ phosphorus-doped polysilicon emitter transistors

This paper analyzes the enhancement of emitter efficiency in in situ phosphorus-doped polysilicon (IDP) emitter transistors, whose polysilicon emitter is crystallized from an in situ phosphorus-doped amorphous Si film. There are two factors that enhance the emitter efficiency of the IDP emitter. One is a potential barrier at the LDP/substrate interface produced by residual stress in the IDP layer. The other is a very thin oxide layer at the interface, which prevents epitaxial growth at the interface. We have distinguished between the emitter efficiency enhancement due to each of these two factors by analyzing the characteristics of three types of IDP emitter in which the residual stress and the thin oxide layer at the interface are controlled differently. We found that the potential barrier due to the residual stress increases the emitter efficiency from about two times to about eight times depending on the emitter size, and that the thin oxide layer at the interface increases the emitter efficiency by about three times     

Decreased low frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors

The effect of hydrogen passivation by forming gas annealing (FGA) on the bipolar junction transistor low frequency noise was investigated. The results demonstrated a reduced 1/f noise component by a factor of five after FGA, which resulted in a reduced corner frequency. An equivalent input noise spectral density (S_IB) dependence on base current (I_B) of S_IBI²_B and on emitter area (A_E) of S_IBA_E⁻¹ was observed, both before and after FGA. The interpretations of the results were (a) the 1/f noise was due to carrier number fluctuation, (b) the noise sources were homogeneously distributed over the polysilicon/monosilicon emitter interfacial oxide, and (c) the noise sources were passivated by hydrogen.     

MODEL AND MODELING OF LOW TEMPERATURE CURRENT GAIN OF POLYSILICON EMITTER BIPOLAR TRANSISTORS

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.     

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented.<>     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz