基于硅基微环谐振器的光学导向逻辑器件

光学导向逻辑器件是采用光开关网络执行逻辑运算的典型应用,光学网络中每一个开关的状态由施加到该开关的电学布尔信号决定。网络中每一个光开关的操作都是独立于其他光开关的操作,并且操作运算结果以光速在网络中传播。因此,光学导向逻辑器件具有非常高的运行速度,且总延迟非常小。硅基微环谐振器由于其尺寸小、功耗低、与CMOS工艺兼容等特性成为构建光学导向逻辑器件的理想单元器件。基于硅基微环谐振器的光学导向逻辑器件很容易实现大规模集成和低成本制备,已经提出并实现的基于硅基微环谐振器的光学导向逻辑器件包括"或/或非"、"与/与非"、"异或/同或"、编码器、译码器和半加器等。回顾了本课题组基于硅基微环谐振器实现的光学导向逻辑器件的研究成果和该领域的最新发展。     

级联谐振微环慢光效应光学陀螺仪灵敏度分析

针对光学陀螺仪灵敏度的问题,设计并研究了一个基于慢光效应的光学陀螺仪。采用微环谐振器级联的结构,根据微环谐振腔工作在谐振波长点时,产生慢光效应,使其可以积累较大的相移,能够探测较低的旋转速度,从而提高陀螺仪灵敏度。实验表明光学陀螺仪灵敏度可以通过改变谐振器耦合系数和微环半径而改变,微环半径从0-90μm增加时,灵敏度随之增加。同样的,灵敏度也随着耦合系数的增加而增加,从而优化光学陀螺仪的灵敏度。     

基于两个级联微环谐振器的电光导向光学译码器

实现了一种基于两个级联微环谐振器的导向光学译码器,器件利用等离子色散效应调制微环谐振器。制作工艺误差引起的两个微环谐振器谐振波长不一致可以通过微环谐振器上热极进行补偿。码型发生器产生的两个电学信号驱动微环谐振器的PIN结,由四个输出端口的光学信号给出译码结果。通过对器件的静态光谱分析得到工作波长和驱动电压。最终实现了100Mbps的动态译码结果。     

串联微环谐振器的光学特性

根据波导耦合方程,导出了串联微环谐振器的传输矩阵,并分析了环数、环间耦合系数以及损耗对串联微环谐振器输出特性的影响。数值模拟表明,串联微环谐振器具有光子带隙的特征。当环数增加时,通带内满足谐振条件的波长数增加;当环间耦合系数增加时,可使通带带宽加宽;通过适当选择环数和环间耦合系数,可以实现滤波和波分复用(WDM)的功能。选用脉冲宽度为50 ps的高斯型激光脉冲注入微环谐振器,发现当环间耦合系数较小时,出射脉冲相对于入射脉冲具有光学延迟的效果,并且随着环数的增加,延迟时间逐渐增大,而当环间耦合系数较大时,光学延迟效果不明显。     

一种有效提高D/A转换器线性指标与分辨率的方法

数模转换器是将接收到的数字信号转换成模拟信号,在系统设计中,其精度非常重要。通常的数模转换器8～16位,目前市场上仅有几款18位数模转换器,但均为音频专用芯片,不适合开发仪器仪表,且价格昂贵。我们采用普通的16位和12位数模转换器AD569与ADC1210设计了一款高分辨率的数模转     

金刚石色心调控及光学谐振器的研究进展

金刚石因其优异的光学特性和色心发射器而被应用于光子器件领域。光学谐振器是一种微纳米光学结构,基于有限模体积内的光-物质相互作用增强,能够将金刚石色心的发射与谐振器的增强效应相结合,有选择性地增强色心的发射,用于在光子电路中提供稳定且强度充足的光学信号。近年来,金刚石微纳加工技术的发展推动了金刚石光学谐振器的研究和应用。本文总结了金刚石光学谐振器的研究现状,概述了金刚石的基本性质、合成与加工方法,介绍了金刚石色心的生成以及其与光学谐振器的耦合原理,梳理了三种不同类型的金刚石光学谐振器的研究进展,并对未来金刚石光学谐振器的发展进行了展望。     

新型微环谐振器双环模型的滤波特性分析

设计了一种新型微环谐振器,其基本结构由圆角正方形波导与条形波导组成.根据波导光学的耦合模理论,推导出双环串联和双环并联的圆角正方形微环谐振器的光强传递函数,并通过数值模拟分别获得这两种模型的谐振器的输出特性.结果表明:与传统的圆环形谐振器相比,圆角正方形结构微环谐振器的输出光谱的通带宽、谐振峰平坦、自由光谱区范围大,更...     

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6+4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.     

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6 4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.     

基于狭缝波导的聚合物基微环折射率传感器研究

基于狭缝波导结构,设计了工作波长在890 nm的聚合物基微环。从折射率传感的角度详细分析了狭缝波导的模场特性。分析了波导高度、宽度及狭缝宽度对灵敏度的影响。传统的狭缝波导具有较高的弯曲损耗,这会影响微环谐振器的品质因子Q以及消光比。设计了非对称的狭缝结构,保证波导模式位于波导中央传输,降低弯曲损耗。为了条形波导与狭缝波导更好的耦合,设计了基于多模干涉结构的条形-狭缝波导模式转换器。仿真表明设计的微环谐振器的传感灵敏度达到109 nm/RIU。     

Silicon micro-ring resonator-based all-optical digital-to-analog converter

All-optical N-bit digital-to-analog converter based on silicon microring resonators (MRRs) and \(1\times 2\) optical splitters, which can convert N-bit optical digital signal to an optical analog signal, is proposed and described in this paper. We design and simulate 2-bit digital-to-analog converter based on two MRRs and two \(1\times 2\) optical splitters. Two optical pump signals represent the two operands of the logical operations to modulate the two MRRs. The proposed silicon MRRs has high extinction ratios of 16.94 and 15.98 dB at very low pump powers of 1.76 and 1.82 mW, respectively.     

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/.     

Chip-scale optical interconnects and optical data processing using silicon photonic devices

Recent advances in the density and complexity of photonic integrated circuits have facilitated possible implementation of chip-scale optical communication systems. Chip-scale optical interconnects and optical data processing are two important functions to transmit and process signal in the optical domain. Silicon photonics offers a promising platform to enable chip-scale optical interconnects and optical data processing using silicon photonic devices. In this paper, we review our recent progress in the design, modeling, and fabrication of silicon photonic devices and their applications in chip-scale optical interconnects and optical data processing with advanced modulation formats. For chip-scale optical interconnects, we experimentally demonstrate digital signal transmissions in silicon microring and silicon vertical slot waveguide. Terabit chip-scale optical interconnect is demonstrated in the experiment. Also, we experimentally demonstrate analog signal transmissions in silicon microring and silicon photonic crystal nanocavity. For chip-scale optical data processing, we experimentally demonstrate all-optical wavelength conversion using a silicon waveguide, simultaneous polarization and wavelength demultiplexing using 2D grating coupler connected with microrings, two-mode (de)multiplexing using a tapered asymmetrical grating-assisted contra-directional coupler, and two-/three-mode (de)multiplexing using asymmetrical directional converter. In addition, we propose and simulate chip-scale optical data exchange, chip-scale high-base optical computing, and chip-scale optical coding/decoding by using nonlinear interactions in a silicon-organic hybrid slot waveguide. The obtained theoretical and experimental results of chip-scale optical interconnects and optical data processing indicate possible integration of optical communication functions on a monolithic chip.     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

An 18-bit high performance audio Σ-△ D/A converter

A multi-bit quantized high performance sigma-delta (Σ-△) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simpler Σ-△ modulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average (DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm2.The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB,respectively.     

Asymmetrically coupled silicon-on-insulator microring resonators for compact add-drop multiplexers

We report on improved filter characteristics of microring resonators (MRs) used as add-drop multiplexers for integrated photonic circuits. By introducing an asymmetrical coupling of the signal waveguides to the resonator, a higher throughput attenuation and drop efficiency is attained. The throughput attenuation is the decisive property for the application of microrings in photonic networks since it determines the crosstalk between drop signal and add signal at the throughput channel of an add-drop multiplexer. Experimental results are compared with analytical relations. MRs with a free-spectral range of 24 nm are fabricated on silicon-on-insulator substrates. A crosstalk reduction by 8.8 dB due to asymmetrical coupling is demonstrated.     

应用于AMOLED源极驱动的高精度DAC设计

针对OLED显示面板更高分辨率、更高精度的需求,本文提出了一种应用于高分辨率AMOLED源极驱动的高精度10bit DAC结构。设计的DAC由6bit的GAMMA校正电阻串DAC及4bit的基于尾电流源插值的输出缓冲器级联构成,达到高精度的同时占用较小的芯片面积。为进一步提高AMOLED驱动的灰阶电压精度,增加了一个DAC斜率可编程单元对线性DAC输出曲线进行进一步调节,以更好地拟合AMOLED显示屏所需的灰阶-电压曲线,此外,输出缓冲器采用尾电流源插值的方法来实现高精度的第二级DAC。在UMC 80nm CMOS工艺下,仿真结果表明设计的DAC的最大INL和DNL分别为0.47LSB、0.24LSB。在10kΩ电阻及30pF电容负载下,DAC电压从最低灰阶到最高灰阶的建立时间为3.38μs。驱动电路可以快速、精确地将图像数据转换为建立在像素电路上的电压,满足分辨率为1080×2 160驱动芯片的应用需求。