激光扫描共焦荧光显微镜的电子控制系统研究

介绍了激光扫描共焦荧光显微镜的电子控制系统,为了提高激光扫描器的定位精度,在系统中提出采用基于闭环象素时钟发生器的检流计振镜所固有的扫描非线性失真补偿方案,减少输出图象的枕形畸变,实现行扫描空间位置的均匀性。在以细分梯形波电流驱动反应式步进电机情况下,根据实测θ-i曲线,用反插法求得与步进电机运行非均匀性相补偿的相电流波,从而获得在小电流情况下高角度均匀的步进电机细分运行特性。     

用于步进电机细分控制的知识人工神经网络

步进电机细分控制中电机绕组电流与电机角度输出是一种非线性函数，其精确拟合是步进电机细分控制中的一个重要课题，应用神经网络对其模拟是一种新尝试。针对前馈神经网络的反向传播（BP）学习算法在逼近非线性函数时收敛速度慢，没有先验知识的缺点，提出利用基于知识的人工神经网络（KBANN）来确定步进电机的最佳细分电流数据。仿真结果表明，KBANN具有精度高、速度快的特点，能够实现步进电机均匀步距的细分控制。     

两相混合式步进电机细分驱动

为了设计一款基于数字信号处理器和功率驱动芯片的两相混合式步进电机细分控制电路,通过分析两相步进电机运行特性及细分驱动原理,使用数字信号处理器计算细分电流数据和产生控制用脉宽调制波形,简化了系统构成。驱动器能明显提高步进电动机的运行精度,改善低频振荡的现象,可实现细分级别的任意设置,能根据不同应用场合使用不同细分数来驱动步进电机。     

基于AT89C51的步进电机恒转矩细分驱动电路的设计

通过合理选择步进电机相绕组细分电流波形，提出并介绍了基于AT89C51单片机控制的斩波恒流均匀细分驱动方案及实现技术。     

步进电机恒力矩均匀细分驱动电路的实现

文章通过合理选择步进电机相绕组细分电流波形 ,提出并详细介绍了基于Intel80C196KB单片机控制的斩波恒流均匀细分驱动方案及实现技术。运行结果表明所设计的驱动器具有细分精度高、运行平稳且噪声小、功耗小、可靠性好、体积小、性价比高等优点。     

基于单片机的步进电机细分技术

介绍了基于单片机的步进电机高精度细分技术,提出了基于AT89C51单片机控制的斩波恒流均匀细分驱动方案及实现方法.运行结果表明,该方法可使步进电机的细分技术提高到一个更高精度的细分水平.     

基于单片机的步进电机细分技术研究

文章介绍了用单片机实现步进电机高精度细分技术,在对现有的步进电机的细分技术方案探讨的同时,提出并介绍了基于AT89C51单片机控制的斩波恒流均匀细分驱动方案及实现技术。运行的结果表明所设计的驱动器具有细分精度高,运行平稳且噪声小、功耗小、可靠性好、体积小和性价比高等优点。     

细分步进电机均匀步距的实现方法

本文通过对步进电机细分特性曲线的研究，提出了一种通过软件编程来实现获得均匀的细分步进电机输出步距的方法。     

步进电机变速控制系统设计

空间光学探测仪器为实现视场扫描、波段转换等功能,往往需要步进电机进行驱动。空间用步进电机要求精度高、功耗低、可靠性高。本文设计了一种基于FPGA的两相步进电机控制系统,采用矢量横幅均匀旋转的方法实现八细分驱动。并根据S曲线算法模拟离散的S曲线加减速算法表,保证电机转子运转速度与加速度变化的连续性,提高电机运行的平稳性能。测试结果表明,该套控制系统功耗低、精度高,很好的完成了设计要求。     

基于80C196MC的步进电机恒转矩细分驱动系统的设计与应用

本文通过合理选择步进电机相绕组细分电流波形，提出并介绍了基于80C196MC单片机控制的步进电机恒转矩斩波恒流细分驱动方案，技术实现及其应用。     

多制式VGA-TV视频转换器的实现

介绍了一种适合标准ＶＧＡ视频和非标准视频的通用视频格式转换器。叙述了采用ＡＬ１２８为核心芯片的转换器硬件结构设计,详细说明了对各种输入格式的视频信号实现自动检测和自动处理的原理和过程。     

Scan test architectures for digital board testers

Boundary scan is a method of implementing test access to the terminals of a component, cluster, or board. Although substituting boundary scan access for direct tester access to these terminals does not alter the concept of digital testing, the replacement of parallel test vectors by serial data streams requires tester support for serial data.This article first considers the problems posed by boundary scan sequences, which are long and contain meaningful vector data, constant data, and irrelevant, or don't care bits, arbitrarily interspersed. We use the model of meaningful data within a frame of constant or irrelevant bits as a means of handling vector data efficiently, and we propose the sequencing and control features of the general-purpose digital tester as an efficient way to implement these frames. Using a specific example, we show that the performance achieved and the data storage resources required compare favorably to approaches based on special-purpose framing hardware.     

考虑测试功耗的扫描链划分新方法

提出考虑测试功耗的扫描链划分新方法.首先为基于扫描设计电路的峰值测试功耗和平均功耗建模,得出测试功耗主要由内部节点的翻转引起的结论,因此考虑多条扫描链情况,从输入测试集中寻找相容测试单元,利用扫描单元的兼容性,并考虑布局信息,将其分配到不同的扫描链中共享测试输入向量,多扫描链的划分应用图论方法.在ISCAS89平台上的实验结果表明,有效降低了峰值测试功耗和平均测试功耗.     

红外点源导引头的分类及工作原理简析

根据红外点源导引头扫描、调制方式的不同,把目前仍广泛使用的红外点源导引头分成如下5类:旋转扫描导引头、圆锥扫描导引头、玫瑰线扫描导引头、四象限探测导引头和十字线探测导引头,并对此5类导引头的工作原理及性能特点进行了简单分析.     

Partial scan flip-flop selection by use of empirical testability

Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.     

SOC的可测试性设计策略

介绍了几种主要的VLSI可测性设计技术,如内部扫描法、内建自测试法和边界扫描法等,论述如何综合利用这些方法解决SOC内数字逻辑模块、微处理器、存储器、模拟模块、第三方IP核等的测试问题,并对SOC的可测性设计策略进行了探讨.     

Deterministic BIST with Multiple Scan Chains

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

JTAG测试中扫描链的配置问题研究

分析了常见扫描链路配置中面临的问题,提出了一种扫描链配置方案。结合工程测试中出现的实际问题,给出了有关扫描链路配置的一些建议和注意事项。     

边界扫描测试结构完备性诊断策略

边界扫描结构完备性测试是在其他任何测试之前建议首先进行的测试操作，以确保边界扫描结构能正常工作。本文在分析了边界扫描结构故障类型与测试原理之后提出了一种完备性诊断策略，并给出了具体实现过程。