Design of a highly PAE class-F power amplifier using front coupled tapered compact microstrip resonant cell

This article presents the design and implementation of a class-F power amplifier (PA) with a low voltage pHEMT, using a novel Front Coupled Tapered Compact Microstrip Resonant Cell (FCTCMRC) for obtaining a high-efficiency performance. The FCTCMRC is used as a harmonic control circuit, which is short and open circuit for the second and third harmonics, respectively. The required dc-supply voltage is low due to application of a low-voltage pHEMT in the circuit implementation. Therefore, the class-F power amplifier is designed with a high power added efficiency (PAE) and compact circuit size. To verify the method, the designed class-F PA is fabricated using a pHEMT at 1.1 GHz. The proposed class-F power amplifier using the FCTCMRC has obtained 86%PAE under 10 dBm input power, which achieves 16% improvement, also, the circuit size including the harmonic control circuit and output matching is decreased about 25%, all in comparison with the designed PA using the conventional CMRC. The measurement results of the fabricated power amplifier are in good agreement with the simulation results, which verifies the proposed design methodology.     

应用于4G-LTE无线通信系统的F类高PAE射频功率放大器

为了有效实现高谐波抑制并提高功率附加效率,提出了一种适用于4G-LTE无线通信系统的高效F类功率放大器。该功率放大器使用了低电压p-HEMT晶体管和小型微带抑制单元,能够在低射频输入功率下产生n次谐波抑制和较高的功率附加效率（power added efficiency,PAE）。采用谐波平衡法对提出的功率放大器进行了仿真分析,并对其进行了实际制造。通过实际测量对仿真结果进行了验证。测量结果显示,提出功率放大器的工作频率为1.8 GHz,带宽为100 MHz,平均PAE为76.9％,且具有2V的极低漏极电压。射频输入功率范围分别为0-12 dBm时,最大输出功率和增益分别为23.4和17.5 dBm。     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

A 0.4–2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.4–2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards’ working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA’s implementation complexity, are presented and explained to investigate the overlapping area of the transistor’s current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40–76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4–2.3 GHz.     

A modified class-F power amplifier with miniaturized harmonic control circuit

In this paper, a modified class-F power-amplifier (PA) for GSM applications is designed, simulated and tested. In this design, novel symmetrical meandered lines compact microstrip resonant cell (SMLCMRC), is proposed as a new harmonics control circuit (HCC), which resulted in size compression, power added efficiency (PAE) enhancement, power gain improvement, and better linearization in the PA. In this work both of the conventional class-F amplifier and proposed amplifier with SMLCMRC is designed at 1.8 GHz. The measurements show that the proposed PA with SMLCMRC has 72.54% maximum PAE, 17.13 dB gain and the 1 dB compression point (P1dB) is about 35.1 dBm. These results show, 16.5% improvement in PAE, 1.33 dB increment in gain and 1.1 dB improvement in linearity operating range of proposed amplifier compared to the conventional PA.     

基于悬置线双模谐振器谐波控制型滤波功放

为了实现高效率的射频滤波功率放大器（filtering power amplifier）,将基于悬置线的截线加载谐振器（stub-loaded resonator）带通滤波器的输入阻抗直接匹配到射频功放管CGH40010F的最佳基波阻抗和谐波阻抗,实现射频功率放大器与滤波器的联合设计,使滤波器同时实现了滤波、阻抗匹配和谐波控制的功能,避免了额外的输出匹配结构,实现了结构紧凑、具有滤波功能的高效率谐波控制型射频功放.实测结果表明在中心频率2.45GHz处,其输出功率约为40dBm,最大电源附加效率（power added efficiency）为76.9%,同时具有良好的滤波特性.     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

应用于S频段的宽带高谐波抑制的F类功率放大器的设计

采用InGaP/GaAs HBT工艺设计了一个适用于S频段的宽带F类功率放大器,管芯大小为3×3×0.82mm3。为了同时实现高谐波抑制和宽带,在宽带匹配电路中使用了谐波陷波器。在1.8~2.5 GHz范围内,该匹配网络的输入阻抗约为一个常电阻,二次谐波阻抗约为零而三次谐波阻抗接近无穷大,因此提高了功率放大器的效率。输入测试信号为连续波,测试结果表明该功率放大器在1dB压缩点下的输出功率约为34dBm,PAE约为57%,2到4次谐波分量功率均小于-53dBc。     

Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 μm GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.     

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.     

High Efficiency RF Power Amplifier Designed With Harmonic Real-Time Active Load-Pull

In this work, a high efficiency p-HEMT radio frequency power amplifier (PA) is designed using a new multiharmonic real-time active load-pull using the large signal network analyzer. This technique synthesizes a large set of instantaneous load mismatches to quickly find the optimal harmonic impedances, so as to achieve high PA efficiency in a shortened design cycle. At 2 GHz a demo power amplifier implemented with a p-HEMT demonstrated a power added efficiency (PAE) of 68.5% for 18.0 dBm output power, while achieving a maximum PAE of 75% below the 1 dB compression point for 18.6 dBm output power.     

基于40 nm CMOS工艺的高效率功率放大器设计

针对硅基毫米波功率放大器存在的饱和输出功率较低、增益不足和效率不高的问题,基于TSMC 40nm CMOS工艺,设计了一款工作在28GHz的高效率和高增益连续F类功率放大器。提出的功率放大器由驱动级和功率级组成。针对功率级设计了一款基于变压器的谐波控制网络来实现功率合成和谐波控制,有效地提高了功率放大器的饱和输出功率和功率附加效率。采用PMOS管电容抵消功率级的栅源电容,进一步提高线性度和增益。电路后仿真结果表明,设计的功率放大器在饱和输出功率为20.5dBm处的峰值功率附加效率54%,1dB压缩点为19dBm,功率增益为27dB,在24GHz~32GHz频率处的功率附加效率大于40%。     

A Wideband 77-GHz, 17.5-dBm Fully Integrated Power Amplifier in Silicon

A 77-GHz,$+$17.5 dBm power amplifier (PA) with fully integrated 50-$Omega$input and output matching and fabricated in a 0.12-$muhbox m$SiGe BiCMOS process is presented. The PA achieves a peak power gain of 17 dB and a maximum single-ended output power of 17.5dBm with 12.8% of power-added efficiency (PAE). It has a 3-dB bandwidth of 15 GHz and draws 165 mA from a 1.8-V supply. Conductor-backed coplanar waveguide (CBCPW) is used as the transmission line structure resulting in large isolation between adjacent lines, enabling integration of the PA in an area of 0.6$hbox mm^2$. By using a separate image-rejection filter incorporated before the PA, the rejection at IF frequency of 25 GHz is improved by 35 dB, helping to keep the PA design wideband.     

一种新型提高射频功率放大器PAE的电路技术

提出了一种新型提高射频功率放大器功率附加效率(PAE)的电路技术,该方法通过滤除二次谐波分量、反射叠加三次谐波分量以提高电路PAE,分析了相位匹配的机制及其影响因素.基于该技术设计了一款功率放大器,仿真结果表明:工作频率为918 MHz时,该功放的P1dB达到了30.05 dBm,功率附加效率达到了58.75%,较普通...     

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

一种自适应线性化偏置的单片集成功率放大器

提出一种自适应线性化偏置的电路结构,通过调节控制电压改变偏置管的工作状态,提高功率放大电路的线性度,降低偏置电流对参考电压和环境温度的敏感度.利用双反馈环结构抑制输入阻抗随频率的变化,实现了宽带匹配,拓展了放大器的带宽.采用微波电路仿真软件AWR进行仿真,验证了带宽范围内的相位偏离度在2°以内.基于2μm InGaP/GaAs HBT工艺,设计了集成电路版图并成功流片.测试结果表明:在3.5V电压供电下,该放大器在1～2.5 GHz频带范围内,输入反射系数均在-10 dB以下,功率增益为23 dB,输出功率大于30 dBm,误差向量幅度在2.412 GHz时为.2.7％@24 dBm,最大功率附加效率达40％.     

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc     

应用于无线传感器网络的功率放大器的设计

给出一种基于TSMC 0.18 μm RF CMOS工艺,应用于无线传感器网络的2.4 GHz 功率放大器的设计.该功率放大 器工作频率范围为2.4 GHz～2.4835 GHz,采用全差分AB类共源共栅电路结构,使用功率控制技术以节省功耗,当输入信号 功率-12.5 dBm时,输出功率在-10.4 dBm至5.69 ...     

Design and Temperature Reliability Testing for A 0.6–2.14GHz Broadband Power Amplifier

This article presents a broadband power amplifier (PA) with a compact structure and investigates its temperature reliability. Design and temperature reliability test procedures are elaborated. The PA delivers good broadband characteristics (0.6–2.14GHz) with the maximum PAE of 46.4 % and saturated output power of more than 35.1dBm at the whole operating frequency band. A series of experiments including those on DC characteristic, S-parameter and large signal characteristic have been conducted to investigate the temperature effects for the broadband performance and reliability of the designed PA.     

基于低通滤波匹配网络的双频功率放大器设计

提出了一种基于低通滤波匹配网络的高效率并发双频功率放大器设计方法。将连续F 类与连续逆F 类功放模式相结合,在保证效率的前提下拓展了阻抗设计空间,同时在谐波范围内引入多个传输零点,完成低通滤 波匹配网络的设计,对谐波进行抑制。为验证设计方法的合理性,设计制造了一款工作于1. 6 GHz 与2. 4 GHz 且带 宽超过200 MHz 的并发高效率功率放大器,在两频带内具有超过66%的功率附加效率以及超过40 dBm 的输出功 率,其相邻信道泄漏比也优于-25 dBc。