小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

二维9/7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9/7小波变换(DWT)Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点.这种并行处理的Mesh结构可提高小波变换电路速度,以及图像压缩的速度.     

一种基于提升的二维离散小波变换VLSI架构

离散小波变换(Discrete Wavelet Transform,DWT)需要较多的运算量以及较大的存储器空间,为了使之适用于实时的图像处理应用,就需要开发特殊的架构和芯片来提高离散小波变换的运算性能。基于提升的二维DWT提出了一种新型的VLSI结构——LLSP架构,其结合逐级和基于行的架构这两者特点,带来了硬件开销和存储器空间的降低,并可以用于多提升步骤的扩展以及多级二维离散小波变换。     

一种适合JPEG2000的离散小波变换VLSI统一结构

提出了一种基于提升算法(1ifting)的离散小波变换(DWT)统一结构。它无需额外的边界延拓过程，经配置后可适用于JPEG2000中的无损或有损小波变换。通过将边界延拓过程内嵌于离散小波变换中，可以降低功耗，减少所需内存。为了达到更高的处理速度和硬件利用率，采用了流水线和折叠结构。这种高效紧凑的离散小波变换结构适用于JPEG2000编码器和各种实时图像／视频应用系统．     

二维离散傅立叶-离散小波混合变换及其在超声波医学图像去噪中的应用

如果二维信号沿水平方向和沿垂直方向的干扰和噪声是异类的,如沿水平方向为窄带频率干扰,而沿垂直方向为高斯白噪声,使用传统的二维离散傅立叶离散变换(2-D Drr)或二维离散小波变换(2-D DWT)可能造成信号成分的丢失和不必要的计算,而采用[1,2]提出的一种混合的二维变换:二维离散傅立叶离散小波混合变换(2-D DFF-DWT),可有效Ё解决异类的干扰和噪声中的信号提取问题.本文在[1,2]的基础上,进一步补充了2-D DFT-DWT的定义和算法,指出这种混合变换可被用来从不同方向去除二维信号中的噪声和干扰.通过这种变换可以结合离散傅立叶变换和离散小波变换二者的优点从干扰和噪声中提取有效信号.本文通过对超声波医学图像去除斑点噪声的具体实例说明了它的应用.     

一种低存储需求的二维DWT VLSI结构设计方法

为了减少基于提升的二维离散小波变换(DWT)VLSI结构设计中的片内存储需求,采用了一种新颖的调度方法,通过读取少量数据进行行滤波操作,并实现和列滤波的并行处理,有效地减少了片内存储容量.此外,行滤波和列滤波变换内部结构采用流水线设计方法,加快了运算速度,提高了硬件资源利用率,减小了电路的规模,并且这种基于提升的9/7离散小波变换二维结构很方便兼容5/3滤波器.经过Verilog HDL仿真验证,结果表明,在50MHz系统时钟下,采用9/7滤波器经3级分解,每秒钟可处理21帧大小为1280×1024×8bit的灰白图像.     

基于整数小波变换和改进嵌入零树编码的图像压缩

整数小波变换(IWT)具有输入输出都是整数、只需进行位内运算、便于硬件实现等优点,特别适于图像的无损压缩;而在有损压缩方面,其效果通常稍逊于传统的离散小波变换(DWT)。为了提高IWT图像有损压缩的性能,该文采用基于提升格式的IWT,结合基于形态膨胀运算的改进嵌入零树小波编码(EZW)方法。实验结果表明,在没有增加运算复杂度的情况下,此算法与传统的DWT相比,提高了峰值信噪比(PSNR),具有较好的有损压缩效果。     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

二维9／7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9／7小波变换（DWT）Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点。这种并行处理的Mesh结构可提高小渡变换电路速度,以及图像压缩的速度。     

CCSDS中二维整数小波变换的FPGA实现方法

CCSDS空间图像压缩标准(CCSDS 122.0-B-1)的核心算法之一是三级二维小波变换,此变换适合用可编程逻辑电路实现。文章介绍了整数9/7小波变换的特点,提出了一种基于FPGA的二维变换快速实现结构,该方法利用FPGA内部Block RAM进行行暂存,实现了行列同时变换的效果,节省了内部寄存器资源,并获得了较高的数据吞吐率。在此基础上,文章还给出了两种适用于不同需求的多级变换架构,并通过仿真验证了其合理性。     

Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme.

Novel architectures for 1-D and 2-D discrete wavelet transform (DWT) by using lifting schemes are presented in this paper. An embedded decimation technique is exploited to optimize the architecture for 1-D DWT, which is designed to receive an input and generate an output with the low- and high-frequency components of original data being available alternately. Based on this 1-D DWT architecture, an efficient line-based architecture for 2-D DWT is further proposed by employing parallel and pipeline techniques, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. This 2-D architecture is called fast architecture (FA) that can perform J levels of decomposition for N * N image in approximately 2N2(1 - 4(-J))/3 internal clock cycles. Moreover, another efficient generic line-based 2-D architecture is proposed by exploiting the parallelism among four subband transforms in lifting-based 2-D DWT, which can perform J levels of decomposition for N * N image in approximately N2(1 - 4(-J))/3 internal clock cycles; hence, it is called high-speed architecture. The throughput rate of the latter is increased by two times when comparing with the former 2-D architecture, but only less additional hardware cost is added. Compared with the works reported in previous literature, the proposed architectures for 2-D DWT are efficient alternatives in tradeoff among hardware cost, throughput rate, output latency and control complexity, etc.     

RNS-FPL merged architectures for orthogonal DWT

Novel, regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1D discrete wavelet transform (DWT) and 1D inverse discrete wavelet transform (1DWT) are presented. These structures halve the number of look-up tables (LUTs) required per octave, providing a sustained throughput independent of the input data and filter coefficient precision. They are suitable to be considered as the core of 2D DWT processors for high data rate image processing applications     

On the Dual-Tree Complex Wavelet Packet and $M$-Band Transforms

The two-band discrete wavelet transform (DWT) provides an octave-band analysis in the frequency domain, but this might not be ldquooptimalrdquo for a given signal. The discrete wavelet packet transform (DWPT) provides a dictionary of bases over which one can search for an optimal representation (without constraining the analysis to an octave-band one) for the signal at hand. However, it is well known that both the DWT and the DWPT are shift-varying. Also, when these transforms are extended to 2-D and higher dimensions using tensor products, they do not provide a geometrically oriented analysis. The dual-tree complex wavelet transform , introduced by Kingsbury, is approximately shift-invariant and provides directional analysis in 2-D and higher dimensions. In this paper, we propose a method to implement a dual-tree complex wavelet packet transform , extending the as the DWPT extends the DWT. To find the best complex wavelet packet frame for a given signal, we adapt the basis selection algorithm by Coifman and Wickerhauser, providing a solution to the basis selection problem for the . Lastly, we show how to extend the two-band to an -band (provided that ) using the same method.     

基于DSP Builder的二维提升小波变换实现

离散小波变换在图像压缩处理中有着重要的作用,并得到了广泛的应用.与传统的基于卷积的架构相比较,基于提升的架构具有需要较少的硬件资源,占用较少的芯片面积等优点.在DSP Builder中实现了基于提升的一维离散小波变换,并通过构造相关的存储器控制逻辑,完成了二维离散小波变换架构的设计.利用该架构对图像进行离散小波变换,与软件变换的结果相比较,并计算出图像的峰值信噪比,验证了其正确性.     

Discrete wavelet transform: data dependence analysis and synthesisof distributed memory and control array architectures

We perform a thorough data dependence and localization analysis for the discrete wavelet transform algorithm and then use it to synthesize distributed memory and control architectures for its parallel computation. The discrete wavelet transform (DWT) is characterized by a nonuniform data dependence structure owing to the decimation operation it is neither a uniform recurrence equation (URE) nor an affine recurrence equation (ARE) and consequently cannot be transformed directly using linear space-time mapping methods into efficient array architectures. Our approach is to apply first appropriate nonlinear transformations operating on the algorithm's index space, leading to a new DWT formulation on which application of linear space-time mapping can become effective. The first transformation of the algorithm achieves regularization of interoctave dependencies but alone does not lead to efficient array solutions after the mapping due to limitations associated with transforming the three-dimensional (3-D) algorithm onto one-dimensional (1-D) arrays, which is also known as multiprojection. The second transformation is introduced to remove the need for multiprojection by formulating the regularized DWT algorithm in a two-dimensional (2-D) index space. Using this DWT formulation, we have synthesized two VLSI-amenable linear arrays of LPEs computing a 6-octave DWT decomposition with latencies of M and 2M-1, respectively, where L is the wavelet filter length, and M is the number of samples in the data sequence. The arrays are modular, regular, use simple control, and can be easily extended to larger L and J. The latency of both arrays is independent of the highest octave J, and the efficiency is nearly 100% for any M with one design achieving the lowest possible latency of M     

Multiview image coding using depth layers and an optimized bit allocation

In this paper, we present a novel wavelet-based compression algorithm for multiview images. This method uses a layer-based representation, where the 3-D scene is approximated by a set of depth planes with their associated constant disparities. The layers are extracted from a collection of images captured at multiple viewpoints and transformed using the 3-D discrete wavelet transform (DWT). The DWT consists of the 1-D disparity compensated DWT across the viewpoints and the 2-D shape-adaptive DWT across the spatial dimensions. Finally, the wavelet coefficients are quantized and entropy coded along with the layer contours. To improve the rate-distortion performance of the entire coding method, we develop a bit allocation strategy for the distribution of the available bit budget between encoding the layer contours and the wavelet coefficients. The achieved performance of our proposed scheme outperforms the state-of-the-art codecs for several data sets of varying complexity.     

一种基于ICA的图像水印方法

本文提出了一种结合离散小波变换(DWT)、离散余弦变换(DCT)和独立分量分析(ICA)的图像数字水印方法。该方法把原始图像进行二维小波分解，保留其高频细节信息，然后对小波逼近子图进行离散余弦变换并嵌入水印。水印的检测使用了ICA方法。实验结果表明该水印方案很好的实现了水印的鲁棒性与不可见性的统一，对各种攻击具有很好的鲁棒性。同时由于ICA方法的引入，较好的改善了水印的检测效果。     

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform

A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages are performed concurrently for transposition-free implementation of 2-D DWT. The proposed design can offer nearly the same throughput rate, and requires the same or less the number of adders and multipliers as the best of the existing structures. The storage space is found to occupy most of the area in the existing 2-D DWT structures but the proposed structure does not require any on-chip or off-chip storage of input samples or storage/transposition of intermediate output. The proposed one, therefore, involves considerably less hardware complexity compared with the existing structures. Apart from that, it has less duration of cycle period in comparison to the existing structures, and has a latency of cycles while all the existing structures have latency of cycles, the filter order being small compared to the input size .