基于RTD与CMOS的新型数字电路设计

纳米电子器件RTD与CMOS电路结合,这种新型电路不仅保持了CMOS动态电路的所有优点,而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟,并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。     

一种高性能InP基谐振隧穿二极管的研制

设计并用分子束外延技术生长了InP基InGaAs/AlAs体系RTD材料,采用传统湿法腐蚀、光学接触式光刻、金属剥离、台面隔离和空气桥互连工艺,研制出了具有优良负阻特性和较高阻性截止频率的InP基RTD单管，器件正向PVCR为17.5,反向PVCR为28,峰值电流密度为56kA/cm^2,采用RNC电路模型进行数据拟合后得到阻性截止频率为82.8GHz，实验为今后更高性能RTD单管的研制,以及RTD与其他高速高频三端器件单片集成电路的设计与研制奠定了基础。     

一种高性能InP基谐振隧穿二极管的研制

设计并用分子束外延技术生长了InP基InGaAs/AlAs体系RTD材料,采用传统湿法腐蚀、光学接触式光刻、金属剥离、台面隔离和空气桥互连工艺,研制出了具有优良负阻特性和较高阻性截止频率的InP基RTD单管.器件正向PVCR为17.5,反向PVCR为28,峰值电流密度为56kA/cm2,采用RNC电路模型进行数据拟合后得到阻性截止频率为82.8GHz.实验为今后更高性能RTD单管的研制,以及RTD与其他高速高频三端器件单片集成电路的设计与研制奠定了基础.     

硅基太赫兹集成电路研究进展北大核心CSCD

太赫兹波处在亚毫米波与远红外光之间,应用于无线通信具有比微波通信更大的传输带宽和传输速率,在大数据无线通信等方面具有巨大的应用潜力。特征频率逐渐达到太赫兹频段的硅基集成电路工艺,为高集成度低成本太赫兹通讯电路的实现提供了可能。本文综述了近年来硅基太赫兹集成电路的研究进展,论述了硅基太赫兹集成电路设计在有源器件模型、互连结构、电路设计方法等方面面临的挑战,并对硅基太赫兹集成电路的发展趋势进行了讨论。     

势阱势垒宽度对GaAs/AlGaAs对称DBS RTD NDR特性的影响

目前共振隧穿二极管(RTD)多值逻辑电路研究采用多个MOSFETs组合,以逼近RTD特性,这是现有逻辑功能验证的不足。针对该问题,通过建立对称双势垒RTD电子输运的解析模型,进而采用SILVACO TCAD对Ga As/Al Ga As基对称DBS RTD器件的电学特性进行仿真实验研究。根据仿真实验的结果分析总结了势阱和势垒宽度对Ga As/Al Ga As基对称DBS RTD负阻特性影响的规律,并根据MVL电路设计应用的低压、低功耗、适当峰谷电流比和工艺可实现性等要求,通过大量的仿真优化实验提出采用Ga As/Al Ga As基对称DBS RTD实现多值逻辑电路设计所需的对称DBS RTD器件设计参数窗口。     

Monolithically Fabricated OEICs Using RTD and MSM

报道了GaAs基共振隧穿二极管(RTD)与金属-半导体-金属光电探测器(MSM PD)单片集成的两种光电集成电路,并在室温条件下分别测试了RTD器件、MSM器件和集成电路的电学特性.测试表明:RTD器件的峰谷电流比为4;由于改进了在半绝缘GaAs衬底上制作MSM的方法,5V偏压下的电流由原来的2μA增加到了18μA,基本实现了两种电路的逻辑功能.     

GaAs基RTD与MSM光电集成

报道了GaAs基共振隧穿二极管(RTD)与金属-半导体-金属光电探测器(MSM PD)单片集成的两种光电集成电路,并在室温条件下分别测试了RTD器件、MSM器件和集成电路的电学特性.测试表明:RTD器件的峰谷电流比为4;由于改进了在半绝缘GaAs衬底上制作MSM的方法,5V偏压下的电流由原来的2μA增加到了18μA,基本实现了两种电路的逻辑功能.     

共振隧穿器件应用电路概述——共振隧穿器件讲座(2)

在“共振隧穿器件概述”的基础上,对共振隧穿器件应用电路作了全面概括的介绍。首先对共振隧穿器件应用电路的特点、分类和发展趋势作了简述;进一步对由RTDH/EMT构成的单-双稳转换逻辑单元(MOBILE)和以它为基础构成的RTD应用电路,包括柔性逻辑、静态随机存储(SRAM)、神经元、静态分频器等电路的结构、工作原理和逻辑功能等进行了介绍。关于RTD/HEMT构成的更为复杂的电路,如多值逻辑、AD转换器以及RTD光电集成电路等将在本讲座最后部分进行讲解。     

RTD基高速多值量化器的设计

建立的RTD SPICE模型,与实际制作的GaAs基RTD器件进行了拟合验证.对四值量化器电路的工作原理进行了解释说明,通过器件参数的提取,对电路进行了模拟仿真,确定了电路相关参数.通过公式计算得出的电路阈值电压与模拟结果一致.最后对电路最大的工作频率进行了分析.     

一种高抗辐射的SOI电脉冲时间间隔测定电路

研制出一种高抗辐射的 SOICMOS电脉冲时间间隔测定器集成电路。在阐述其工作原理的基础上 ,进行了抗辐射设计与版图设计。通过实验分析找到了向 SOI材料的 Si O2 埋层注入 F+ 离子的优化注入条件 ,有效地抑制 SOI CMOS器件的阈值电压的漂移 ,提高了电路的抗辐射性能。采用注入 F+离子 SOICMOS工艺投片后测试结果表明 :该电路与同类体硅电路相比 ,具有高速、低功耗、测量精度高以及优良的抗辐射性能     

Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing

The resonant tunneling diode (RTD) has found numerous applications in high-speed digital and analog circuits due to the key advantages associated with its folded back negative differential resistance (NDR) current-voltage (I-V) characteristics as well as its extremely small switching capacitance. Recently, the RTD has also been employed to implement high-speed and compact cellular neural/nonlinear networks (CNNs) by exploiting its quantum tunneling induced nonlinearity and symmetrical I-V characteristics for both positive and negative voltages applied across the anode and cathode terminals of the RTD. This paper proposes an RTD-based CNN architecture and investigates its operation through driving-point-plot analysis, stability and settling time study, and circuit simulation. Full-array simulation of a 128 $,times,$128 RTD-based CNN for several image processing functions is performed using the Quantum Spice simulator designed at the University of Michigan, where the RTD is represented in SPICE simulator by a physics based model derived by solving SchrÖdinger's and Poisson's equations self-consistently. A comparative study between different CNN implementations reveals that the RTD-based CNN can be designed superior to conventional CMOS technologies in terms of integration density, operating speed, and functionality.      

由RTD/MOSFET构成的压控振荡器的设计与实现

提出了一种基于负阻器件共振隧穿二极管(RTD)与MOSFET结合的新型压控振荡器(VCO),并利用了高级设计系统(ADS)软件对该振荡器的可行性进行了电路仿真,利用分立RTD、MOSFET器件实现了此种VCO,实际调频范围在20～26 MHz之间。RTD与三端器件的连接方式不同可呈现不同的调制I-V特性,这种调制特性对基于RTD的振荡电路的频率也会产生影响。通过深入研究这种调制对振荡电路频率产生的影响,得到多种不同于常规方法的电压控制频率方式,其中一些具有很好的线性度。因此该电路的研究对于RTD在高频、高速振荡电路中的进一步应用具有重要意义。     

Operation Limits for RTD-Based MOBILE Circuits

Resonant-tunneling-diode (RTD)-based MOnostable–BIstable Logic Element (MOBILE) circuits operate properly in a certain frequency range. They exhibit both a minimum operating frequency and a maximum one. From a design point of view, it should be desirable to have gates with a correct operation from dc up to the maximum operating frequency (i.e., without the minimum bound). This paper undertakes this problem by analyzing how transistors and RTDs interact in RTD-based circuits. Two malfunctions have been identified: the incorrect evaluation of inputs and the lack of self-latching operation. The difficulty to study these problems in an analytical way has been overcome by resorting to series expansions for both the RTD and the heterojunction field-effect transistor $I$–$V$ characteristics in the points of interest. We have obtained analytical expression linking representative device parameters and technological setup, for a MOBILE-based circuit to operate correctly.      

基于共振隧穿二极管的TSRAM设计

介绍了基于共振隧穿二极管的隧穿静态随机存储器的单元结构和原理.讨论了nMOS,pMOS和CMOS作为单元里的选中管的特点,综合考虑面积和功耗后,发现nMOS是选中管的最佳选择.设计了基于RTD的TSRAM系统结构.模拟显示了这种新型存储器具有高集成度、高速和低功耗的优势.     

A new RTD-FET logic family

We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Monolithic integrated resonant tunneling diode and heterostructure junction field effect transistor circuits

We have developed a simple technology for monolithic integration of resonant tunneling diodes (RTDs) and heterostructure junction-modulated field effect transistors (HJFETs). We have achieved good device performance with this technology: HJFETs had transconductances of 290 mS/mm and current densities of 310 mA/mm for a 1.5 μm gate length; RTDs had room temperature peak to valley ratios greater than 20:1 with current densities of 42 kA/cm². With this technology, we have demonstrated a monolithically integrated RTD + HJFET state holding circuit that can serve as a building block circuit for self-timed logic units. This circuit is resistor-free and operates at room temperature. The state holding circuit showed large noise margins of 1.21 V and 0.71 V, respectively, for input low and input high, for a 1.7 V input voltage swing. We have examined the transient response of the circuit and investigated the effect of circuit design parameters on propagation delay. We identify the RTD valley current as the limiting factor on propagation delay. We discuss the suitability of RTD + HJFET circuits such as our state holding circuit for highly dense integrated circuits.