GaN E-D HEMT集成逻辑门电路特性研究

基于金属有机化学气相沉积(MOCVD)生长的高质量AlGaN/GaN异质结构材料,采用选择性栅挖槽结合栅介质工艺实现GaN增强型/耗尽型(E/D)HEMT器件的集成,应用直接耦合场效应管逻辑(DCFL)设计并研制GaN E/D HEMT集成逻辑门电路。通过对GaN E/D器件性能以及逻辑门电路性能的分析讨论,研究了GaN E/D器件性能对逻辑门电路性能的影响。同时还对选择性栅挖槽结合栅介质工艺实现GaN E/D器件存在的问题进行了分析讨论。     

蓝宝石衬底上槽栅型X波段增强型AlGaN/GaN HEMT

研制了一款X波段增强型AlGaN/GaN高电子迁移率晶体管(HEMT)。在3英寸(1英寸=2.54 cm)蓝宝石衬底上采用低损伤栅凹槽刻蚀技术制备了栅长为0.3μm的增强型AlGaN/GaN HEMT。所制备的增强型器件的阈值电压为0.42 V,最大跨导为401 mS/mm,导通电阻为2.7Ω·mm。器件的电流增益截止频率和最高振荡频率分别为36.1和65.2 GHz。在10 GHz下进行微波测试,增强型AlGaN/GaN HEMT的最大输出功率密度达到5.76 W/mm,最大功率附加效率为49.1%。在同一材料上制备的耗尽型器件最大输出功率密度和最大功率附加效率分别为6.16 W/mm和50.2%。增强型器件的射频特性可与在同一晶圆上制备的耗尽型器件相比拟。     

E/D型HEMT DCFL倒相器

<正> 一、引言为了满足超高速计算机、高速数据处理和卫星通信等高性能电子系统的迫切需要,人们一直在寻求和开发新的超高速和微波器件。利用异质界面二维电子气(2DEG)高迁移率特性的高电子迁移率晶体管(HEMT)及其IC已显示出巨大的发展潜力和广阔的应用前景。因而成为最有希望的候选者之一。以增强型(E型)HEMT为开关管、耗尽型(D型)HEMT(或饱和电阻)为负载的E/D(或E/R)型直接耦合场效应晶体管逻辑     

GaN HEMT电力电子器件技术研究进展

GaN高电子迁移率晶体管(HEMT)器件由于其击穿场强高、导通电阻低等优越的性能,在高达650 V额定电压等级的高效、高频转换器中有着广泛的应用前景。GaN HEMT器件的特性优势与其工艺结构、材料特性密切相关。介绍了耗尽型、增强型GaN HEMT的典型器件结构,并将国内外对结构设计以及材料优化等关键技术问题的研究现状进行了综述,并概括总结了GaN HEMT的技术发展趋势和最新参数指标。     

标准氟离子注入实现增强型GaN基功率器件

介绍了一种直接利用离子注入机对AlGaN/GaN高电子迁移率晶体管(HEMT)器件的栅下进行氟(F)离子注入的方法,成功实现了增强型HEMT器件,阈值电压从耗尽型器件的-2.6V移动到增强型器件的+1.9V.研究了注入剂量对器件性能的影响,研究发现随着注入剂量的不断增加,阈值电压不断地正向移动,但由于存在高能F离子的注入损伤,器件的正向栅极漏电随着注入剂量的增加而不断上升,阈值电压正向移动也趋于饱和.因此,提出采用在AlGaN/GaN异质结表面沉积栅介质充当能量吸收层,降低离子注入过程中的损伤,成功实现了阈值电压为+3.3 V,饱和电流密度约为200 mA/mm,同时具有一个较高的开关比109的增强型金属-绝缘层-半导体HEMT (MIS-HEMT)器件.     

面向下一代GaN功率技术的超薄势垒AlGaN/GaN异质结功率器件

Al GaN/GaN异质结型功率电子器件具有高工作温度、高击穿电压、高电子迁移率等优点,在推动下一代功率器件小型化、智能化等方面具有很大的材料和系统优势。从5种实现增强型GaN基功率电子器件的方法入手,重点介绍了采用超薄势垒Al GaN(小于6 nm)/GaN异质结实现无需刻蚀Al GaN势垒层的GaN基增强型器件的物理机理和实现方法。同时介绍了在超薄势垒Al GaN/GaN异质结构上实现增强型/耗尽型绝缘栅高电子迁移率晶体管单片集成的研究进展,进一步论证了在大尺寸Si基Al GaN/GaN超薄势垒平台上同片集成射频功率放大器、整流二极管、功率三极管等器件的可行性,为Si基GaN射频器件、功率器件、驱动和控制电路的单片集成奠定了技术基础。     

增强型AlGaN/GaN HEMT器件工艺的研究进展

随着高压开关和高速射频电路的发展,增强型GaN基高电子迁移率晶体管(HEMT)成为该领域内的研究热点。增强型GaN基HEMT只有在加正栅压才有工作电流,可以大大拓展该器件在低功耗数字电路中的应用。近年来,国内外对增强型GaN基HEMT阈值电压的研究主要集中以下两个方面:在材料生长方面,通过生长薄势垒、降低Al组分、生长无极化电荷的AlGaN/GaN异质材料、生长InGaN或p-GaN盖帽层,来控制二维电子气浓度;在器件工艺方面,采用高功函数金属、MIS结构、刻蚀凹栅、F基等离子体处理,来控制表面电势,影响二维电子气浓度。从影响器件阈值电压的相关因素出发,探讨了实现和优化增强型GaN基HEMT的各种工艺方法和发展方向。     

复合沟道氟离子增强型AlGaN/GaN HEMT的研究

提出一种复合沟道氟离子(F-)增强型AlGaN/GaN HEMT(Hybrid-channel enhancement-mode AlGaN/GaN HEMT,HCE-HEMT)新结构。该结构引入高、低浓度F-复合沟道,其中高浓度F-注入区位于沟道靠近源漏两端以调制阈值电压,获得增强型器件;低浓度F-区位于沟道中部以调制肖特基栅电极的正向开启电压,增加器件承受的栅电压摆幅,但它对其下方二维电子气的耗尽作用很弱。同时,高浓度区只占栅长的40%,减轻高浓度F-对沟道的影响,提升器件的电流能力。利用Sentaurus软件仿真,结果显示,与传统F-增强型AlGaN/GaN HEMT相比,HCE-HEMT载流能力提高了40.3%,比导通电阻下降了23.3%,同时反向耐压仅下降了5.3%。     

采用耗尽型作负载的高性能N型沟道MOS大规模集成电路

采用耗尽型MOS场效应晶体管(MOSFET)作为负载元件的含意已有认识,且提出了某些器件结构。然而在一个片子上同时制作增强型及耗尽型两种MOSFET是难行的。本文描述采用N型沟道增强型及耗尽型MOSFET的新颖的高速集成电路。集成电路的剖面图示于图1。增强型MOSFET具有一覆盖在热生长二氧化硅的三氧化二铝层来作为栅绝缘物。其阈值电压可由改变二氧化硅与三氧化二铝层的厚度比(SiO_2/Al_2O_3)来控制,直到+1伏、+5伏电源电压均能工作时,这些增强型MOSFET的电     

科锐推出S波段GaN器件,实现雷达应用的效率最大化

正全新60 W GaN HEMT Psat晶体管帮助降低军用和民用雷达系统对于高功率放大器尺寸、重量以及散热的要求。2012年7月9日,科锐公司宣布推出可适用于军用和商用S波段雷达中的高效GaN HEMT晶体管。新型S波段GaN HEMT晶体管的额定功率为60W,频率为3.1至3.5 GHz之间,与传统Si或GaAs MESFET器件相比,能够提供优     

Monolithically integrated enhancement/depletion-mode AIGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

Characterization of heterostructure complementary MISFET circuits employing the new gate current model

A complementary logic circuit employing heterostructure MISFET's is shown to have a larger logic swing and noise margin than an E/D MESFET logic circuit. The noise margin is calculated using a new gate current model that is derived by taking into account the small surface potential dependence on the gate voltage at the heterointerface. The circuit simulation indicates that, for multi-input logic gates, a NAND gate configuration is superior to a NOR gate configuration from the viewpoints of noise margin and switching speed. The normalized high- and low-level noise margins are comparatively balanced (34 and 49 percent) for a three-input NAND gate. For a fan-in/fan-out of 3/3 and a 100-fF wiring capacitance condition, a 54-ps delay time and 57-μW power dissipation/gate at a 100-MHz clock frequency are possible for a NAND gate with 0.5-μm gate-length MISFET's at 77 K.     

High-Temperature Operation of AlGaN/GaN HEMTs Direct-Coupled FET Logic (DCFL) Integrated Circuits

This letter presents the high-temperature performance of AlGaN/GaN HEMT direct-coupled FET logic (DCFL) integrated circuits. At 375 degC, enhancement-mode (E-mode) AlGaN/GaN HEMTs which are used as drivers in DCFL circuits exhibit proper E-mode operation with a threshold voltage (V_TH) of 0.24 V and a peak current density of 56 mA/mm. The monolithically integrated E/D-mode AlGaN/GaN HEMTs DCFL circuits deliver stable operations at 375 degC: An E/D-HEMT inverter with a drive/load ratio of 10 exhibits 0.1 V for logic-low noise margin (NM_L) and 0.3 V for logic-high-noise margin (NM_H) at a supply voltage (V_DD) of 3.0 V; a 17-stage ring oscillator exhibits a maximum oscillation frequency of 66 MHz, corresponding to a minimum propagation delay ( tau_pd) of 446 ps/stage at V_DD of 3.0 V     

Planar integration of E/D-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

A planar-fabrication technology for integrating enhancement/depletion (E/D)-mode AlGaN/GaN high-electron mobility transistors (HEMTs) has been developed. The technology relies heavily on CF/sub 4/ plasma treatment, which is used in two separate steps to achieve two objectives: 1) active device isolation and 2) threshold-voltage control for the enhancement-mode HEMT formation. Using the planar process, depletion- and enhancement-mode AlGaN/GaN HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter is demonstrated. Compared with the devices fabricated by a standard mesa-etching technique, the HEMTs by a planar process have comparable dc and RF characteristics with no obvious difference in the device isolation. The device isolation by a plasma treatment remains the same after 400 /spl deg/C annealing, indicating a good thermal stability. At a supply voltage (V/sub DD/) of 3.3 V, the E/D-mode inverters show an output swing of 2.85 V, with the logic-low and logic-high noise margins at 0.34 and 1.47 V, respectively.     

F等离子体处理增强型及耗尽型AlGaN/GaN HEMT集成SRAM单元电路和电平转换电路

我们设计并且制备了GaN基增强型/耗尽型（E/D 模）直接耦合6管静态随机存取存储器（SRAM）单元电路和电平转换电路。利用氟等离子处理工艺,使用适中的AlGaN势垒层厚度异质结材料,增强型和耗尽型铝镓氮/氮化镓 HEMTs被集成在了同一个晶片上。六管SRAM单元由对称的两个E/D模反相器和增强型开关管组成。在1V的工作电压下,SRAM单元电路的输出高电平和低电平分别为0.95V和0.07V。电平转换电路的工作电压为+6V和-6V,通过4个串联的镍-铝镓氮/氮化镓肖特基二极管使电压降低。通过轮流控制电平转换电路的两个反相器模块的开关状态,电平转换电路输出两路电压,分别为-0.5V和-5V。电平转换器的翻转电压为0.76V。SRAM单元电路和电平转换电路都能正确地工作,展现了氮化镓基E/D模数字和模拟集成电路的潜力。提出了几条设计上的考虑,以避免阈值电压的漂移对电路工作造成的影响。     

含有Al组分阶变AlGaN过渡层的Si基AlGaN/GaN HEMT

采用一个AlN缓冲层和两个Al组分阶变的AlGaN过渡层作为中间层,在76.2mm Si衬底上外延生长出1.7μm厚无裂纹AlGaN/GaN异质结材料,利用原子力显微镜、X射线衍射、Hall效应测量和CV测量等手段对材料的结构特性和电学性能进行了表征。材料表面平整光滑,晶体质量和电学性能良好,2DEG面密度为1.12×1013cm-2,迁移率为1 208cm2/(V.s)。由该材料研制的栅长为1μm的AlGaN/GaN HEMT器件,电流增益截止频率fT达到10.4GHz,这些结果表明组分阶变AlGaN过渡层技术可用于实现高性能Si基GaN HEMT。     

Integrated circuits using fully solution-processed organic TFT devices with printed silver electrodes

We have demonstrated fully solution-processed inverter, NAND and NOR circuits using pseudo-CMOS logic and p-type organic TFT devices with printed electrodes that were fabricated using ink-jet printed silver nanoparticle inks at low temperatures. In order to optimize the gate electrode profiles, we thoroughly assessed the surface wettability of the silver nanoparticle inks. The pseudo-CMOS inverter circuit exhibited exceptional switching characteristics with a high signal gain of 34 at a supply voltage of 20 V. The NAND and NOR circuits also exhibited excellent logic characteristics, whereby the switching voltage was approximately V_DD/2 with a high noise margin and short delay time of 12.5 ms.     

AlGaN/GaN metal-oxide semiconductor heterostructure field-effect transistor with photo-chemical-vapor deposition SiO<Subscript>2</Subscript> gate oxide

High-quality SiO₂ was successfully deposited onto GaN by photo-chemicalvapor deposition (photo-CVD) using a D₂ lamp as the excitation source. The AlGaN/GaN metal-oxide semiconductor, heterostructure field-effect transistors (MOSHFETs) were also fabricated with photo-CVD oxide as the insulating layer. Compared with AlGaN/GaN metal-semiconductor HFETs (MESHFETs) with similar structure, we found that we could reduce the gate-leakage current by more than four orders of magnitude by inserting the photo-CVD oxide layer in between the AlGaN/GaN and the gate metal. With a 2-μm gate, it was found that the saturated I_ds, maximum g_m, and gate-voltage swing (GVS) of the fabricated nitride-based MOSHFET were 512 mA/mm, 90.7 mS/mm, and 6 V, respectively.     

High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

We report a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500/spl deg/C. Starting with a conventional depletion-mode HEMT sample, we found that fluoride-based plasma treatment can effectively shift the threshold voltage from -4.0 to 0.9 V. Most importantly, a zero transconductance (g/sub m/) was obtained at V/sub gs/=0 V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At V/sub gs/=0 V, the off-state drain leakage current is 28 /spl mu/A/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 /spl mu/m-long gate exhibit a maximum drain current density of 310 mA/mm, a peak g/sub m/ of 148 mS/mm, a current gain cutoff frequency f/sub T/ of 10.1 GHz and a maximum oscillation frequency f/sub max/ of 34.3 GHz.