Design and Analysis of Tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) with Enhanced Performance and Its Application in Filters

This paper proposes a high performance tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) where transconductance of VDIBA is enhanced by using programmable positive feedback technique and bandwidth is enhanced by using resistive compensation technique. The enhanced performance of proposed VDIBA is demonstrated by presenting detailed frequency analysis. Furthermore, it is verified that transconductance of proposed VDIBA can be enhanced up to 10.6 mS at tuning current (Ic) of 100 µA. Moreover, resistive compensation technique enhance bandwidth of propose circuit up to 263 MHz. To illustrate the effectiveness of proposed circuit, voltage mode universal biquad filter is designed as an application example. The pole frequency of proposed filter is tunable in range of 10.5–83.4 MHz. The proposed VDIBA and its filter applications are designed and simulated using TSMC 0.18 µm CMOS technology in Cadence virtuoso schematic composer at ± 0.6 V supply voltage.     

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500 μA with offset of 2.2 nA, input resistance of 235 Ω, output resistance of 117 kΩ, current transfer ratio of 0.98, dissipates 0.83 mW power and exhibits bandwidth of 656 MHz which increases to 1.52 GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13 μm technology with a supply voltage of ±0.5 V.     

Improving GBW product on CMOS operational transconductance amplifiers by interleaved feedforward paths

This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

New CMOS realization of high performance Voltage Differencing Inverting Buffered Amplifier and its filter application

This paper describes a high performance voltage differencing inverting buffered amplifier (VDIBA). The transconductance of the proposed circuit is enhanced by using positive feedback technique with only two extra transistors used in active load. Moreover, the bandwidth of proposed circuit is enhanced by using resistive compensation technique. The performance of proposed VDIBA is demonstrated by detailed frequency analysis. Furthermore, it is shown that the transconductance can be enhanced up to 4.61 mS at biasing current of 300 µA. In addition, a third order low pass filter is given as an application example to confirm the high performance of the proposed VDIBA. The proposed low pass filter operates at natural pole frequency of 15 MHz. The proposed VDIBA and its filter application are implemented using TSMC 90 nm CMOS technology in Cadence virtuoso schematic composer at ±0.6 V supply voltage.     

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 μm process parameters. The ac simulation results of amplifier show that GBW is 9 MHz and power consumption is 0.5 mW.     

Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C filter

This paper presents an ultra low voltage, high performance Operational Transconductance Amplifier (OTA) and its application to implement a tunable Gm-C filter. The proposed OTA uses a 0.5 V single supply and consumes 60 μw. Employing special CMFF and CMFB circuits has improved CMRR to 138 dB in DC. Using bulk driven input stage results in higher linearity such that by applying a 500 mv_p-p sine wave input signal at 2 MHz frequency in unity gain closed loop configuration, third harmonic distortion for output voltage is −46 dB and becomes −42.4 dB in open loop state for 820 mv_p-p output voltage at 2 MHz. DC gain of the OTA is 47 dB and its unity gain bandwidth is 17.8 MHz with 20 pF capacitance load due to both deliberately optimized design and special frequency compensation technique. The OTA has been used to realize a wide tunable Gm-C low-pass filter whose cutoff frequency is tunable from 1.4 to 6 MHz. Proposed OTA and filter have been simulated in 0.18 μm TSMC CMOS technology with Hspice. Monte Carlo and temperature dependent simulation results are included to forecast the mismatch and temperature effects after fabrication process.     

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 µm TSMC CMOS technology. The Simulation results show a gain of 18.2 dB, an IIP3 of −4.32 dBm and a noise figure of 3.38 dB at 2.4 GHz. The proposed LNA consumes only 967 µW from a 1-V supply.     

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1 V and its dynamic range is ±1 V too. The designed circuit is simulated in an industrial 65 nm CMOS process. The linear version is tunable over the wide resistance range of 7 kΩ–37 GΩ.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15 MHz LP bandwidth, 2–8 MHz CBP bandwidth and 0–36 dB gain range with 1 dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65 nm CMOS. It achieves 15.2 dB m/27.1 dB m IB/OB-IIP3, −2 dB m IP1dB and 71 dB m IIP2 while consuming 3.6–9.1 mW from a 1.2 V power supply and 0.75 mm² chip area.     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

0.8 V PLL-based automatic frequency tuning system for current-mode filters

A wide-range automatic frequency tuning system for current-mode filters is proposed in this paper. The cutoff frequency of the tunable filter is controlled by an external reference signal and is locked in the desired frequency through a current-mode based phase locked loop (PLL) circuit. Although the PLL operates in a relatively narrow band, the total tuning range of the topology is extended by interpolating an automatic frequency detector after the reference input and before the PLL. The use of current controlled oscillator, based on same blocks with those in the filter, offers accuracy and feasible design in the control path. The topology has been simulated using MOS transistor models for a 130 nm CMOS technology in 0.8 V supply voltage. The achieved overall automatic tuning range was from 2.3 MHz to 660 MHz.     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

A new ultra low-power,universal OTA-C filter in subthreshold region using bulk-drive technique

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans-resistance and trans-conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I_a = 50 nA, I_b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans-conductance (g_m) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter.     

A low-transconductance OTA with improved linearity suitable for low-frequency Gm-C filters

A fully differential operational transconductance amplifier is presented in this paper with enhanced linearity and low transconductance, suitable for low-frequency Gm-C filters. This paper also proposes a new common-mode feedback scheme that presents low sensitivity to large differential voltage swings at the OTA outputs. The proposed OTA was employed in the design of a fully-integrated Gm-C low-pass filter with a cutoff frequency of 30 kHz. The Gm-C filter was fabricated in a 0.35 μm CMOS technology and presented a THD at the output less than 1% for input signals with differential amplitudes up to 3.2 V.     

Stabilization of a superfluorescent fiber source with high performance erbium doped fibers

A high stability superfluorescent fiber source with mean-wavelength stability of 1.3 ppm/°C over a temperature range of 100 °C is proposed based on spectral shaping combined with a thermal management unit. A thermal tunable filter combined with an unpumped filtering erbium-doped fiber is used as the single-pass backward filter. Theoretical model of the filtering fiber’s temperature dependent gain spectra is presented which decides the filter’s central-wavelength with minimum thermal sensitivity for a specific temperature change. Power efficiency and spectral bandwidth of the superfluorescent fiber source are optimized based on three different erbium-doped fibers at room temperature.     

A wideband balun–LNA

In this paper a wideband Low Noise Amplifier (LNA) is introduced which also converts the single-ended input to differential signal at the output. It is based on common-source amplifier with active-feedback to provide input matching. The proposed amplifier has the input matched from 500 MHz to 2.5 GHz. It achieves the maximum voltage gain of 24 dB in this band, while the minimum noise figure (NF) is 2.35 dB. The simulated OIP3 of this amplifier is equal to 21 dBm. The LNA has been designed and simulated in a 0.18 μm CMOS process.     

A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V_pp differential input is improved from ?42 dB to ?55 dB while operating from 1.0 V supply. As an example of the applications of the proposed transconductor, a 4th-order 5 MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130 nm CMOS process. It achieves THD of ?53 dB for 0.4V_pp differential input. It consumes 345 μw from 1.0 V single supply. Theoretical and simulated results are in good agreement.