An architecture for a VLSI FFT processor

We propose a new VLSI architecture for an FFT processor. Our architecture uses few processing elements and can be laid out in a mesh-interconnected pattern. We show how to compute the discrete Fourier transform at n points with an optimal speed-up as long as the memory is large enough. The control is shown to be simple and easily implementable in VLSI.     

基于FPGA流水线结构并行FFT的设计与实现

根据实时信号处理的需求,提出了一种基于FPGA的512点流水线结构快速傅里叶变换(FFT)的设计方案,采用4个蝶形单元并行处理,在Xilinx公司的Virtex7系列的FPGA上完成设计.处理器将基2算法与基4算法相结合,蝶形运算时把乘法器IP核的旋转因子输入端固定为常数,而中间结果用FIFO缓存.采用硬件描述语言verilog完成设计,并进行综合、布局布线,测试结果与MATLAB仿真结果相吻合.     

An image multiresolution representation for lossless and lossycompression

We propose a new image multiresolution transform that is suited for both lossless (reversible) and lossy compression. The new transformation is similar to the subband decomposition, but can be computed with only integer addition and bit-shift operations. During its calculation, the number of bits required to represent the transformed image is kept small through careful scaling and truncations. Numerical results show that the entropy obtained with the new transform is smaller than that obtained with predictive coding of similar complexity. In addition, we propose entropy-coding methods that exploit the multiresolution structure, and can efficiently compress the transformed image for progressive transmission (up to exact recovery). The lossless compression ratios are among the best in the literature, and simultaneously the rate versus distortion performance is comparable to those of the most efficient lossy compression methods.     

An efficient locally pipelined FFT processor

The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log/sub 4/N-1 and adders 2log/sub 4/N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented.     

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.     

An analysis of some common scanning techniques for lossless imagecoding

Though most image coding techniques use a raster scan to order pixels prior to coding, Hilbert and other scans have been proposed as having better performance due to their superior locality preserving properties. However, a general understanding of the merits of various scans has been lacking. This paper develops an approach for quantitatively analyzing the effect of pixel scan order for context-based, predictive lossless image compression and uses it to compare raster, Hilbert, random and hierarchical scans. Specifically, for a quantized-Gaussian image model and a given scan order, it shows how the encoding rate can be estimated from the frequencies with which various pixel configurations are available as previously scanned contexts, and from the corresponding conditional differential entropies. Formulas are derived for such context frequencies and entropies. Assuming an isotropic image model and contexts consisting of previously scanned adjacent pixels, it is found that the raster scan is better than the Hilbert scan which is often used in compression applications due to its locality preserving properties. The hierarchical scan is better still, though it is based on nonadjacent contexts. The random scan is the worst of the four considered. Extensions and implications of the results to lossy coding are also discussed.     

一种异步快速傅立叶变换处理器设计

针对一种异步实现结构的异步快速傅立叶变换处理器,给出了处理器中异步加法器的电路和异步乘法器的结构．该异步快速傅立叶变换处理器采用本地的握手信号代替了传统的整体时钟．通过对一个8点的异步快速傅立叶变换处理器电路仿真,得到该处理器的平均响应时间为31．15ns,仅为最差响应时间42．85ns的72．7％．由此可见,异步快速傅立叶变换处理器在性能方面较同步处理器存在优势。     

An all-optical network architecture

A novel photonic network, MATRIX (for multi-wavelength all-optical transparent information exchange), is proposed in this paper. The all-optical multihop network supports wavelength continuity and provides a very high network capacity. Spatial reuse of wavelengths as well as the multiplicity of fibers in optical fiber cables are exploited and enable the interconnection of N² network nodes with merely N wavelengths. The node structure is simple since neither tunable devices nor wavelength converters are required. Packets are routed through the network by photonic fast packet switching as well as by wavelength and experience a maximum hop number of two. Multiple optical paths between any pair of nodes provide a good network survivability     

一种加窗插值FFT谐波分析方法

由于很难实现同步采样和整周期截断,因此,利用FFT算法分析电网谐波信号时存在频谱泄露和栅栏效应,影响算法的分析精度。加窗插值FFT是抑制频谱泄露和消除栅栏效应的有效方法,在此提出一种基于3项3阶Nuttall窗插值FFT的谐波分析方法,推导了插值系数公式以及各次谐波的频率、幅值和相位的修正公式。对该算法与Hanning窗、Blackman窗插值FFT算法进行Matlab仿真对比研究,验证了该算法具有更高的分析精度。     

An Efficient FFT Engine With Reduced Addressing Logic

In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 $N$-point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a CMOS 0.18 $mu{rm m}$ technology. The circuit gate count analysis indicates that significant logic reduction can be achieved with improved throughput compared to the conventional implementations.      

FFT算法的一种FPGA实现

FFT运算在OFDM系统中起调制和解调的作用。针对OFDM系统中FFT运算的要求，研究了一种易于FPGA实现的FFT处理器的硬件结构。接收单元采用乒乓RAM结构，扩大了数据吞吐量。中间数据缓存单元采用双口RAM，减少了访问RAM的时钟消耗。计算单元采用基2算法，流水线结构，可在4个时钟后连续输出运算结果。各个单元协调一致的并行工作，提高了系统时钟频率，达到了高速处理。采用块浮点机制，动态扩大数据范围，在速度和精度之间得到折衷。模块化设计，易于实现更多点数的FFT运算。     

An introduction to FFT and time domain windows

This paper includes a brief tutorial on digital spectrum analysis and FFT-related issues to form spectral estimates on digitized signals. Some review of the DFT has been presented, and some discussion on the computational advantages of the FFT calculation has also been presented. Finally, the main considerations on windowing and window characteristics have been briefly discussed.     

高基FFT处理器高效地址产生算法

FFT算法是数字信号处理最常用算法,使用FFT处理器是进行FFT运算的重要手段之一。本文针对主基16局部流水的FFT处理器,提出了一种运用于高基FFT处理器的新型地址产生结构,能够进行16~4096点可变长的FFT运算,具有快速灵活的特点,且结构简单,适合FFT处理器中对数据通路控制的实现。     

一种改进的滑动窗FFT递推算法

在信号谱线分析中,经常用到滑动窗的FFT计算,由于传统的FFT在N值较大和滑动步进较小时,计算量较大,在实时通信系统中难以实现,本文提出一种连续滑动窗的递推FFT算法,该算法充分利用了前窗的计算结果并将输入序列转换为一个输入端仅有少数非零点的特殊序列,不仅降低了计算量,而且提高了使用的灵活性和实时性。     

高效可配置浮点FFT处理器设计

为了克服高精度浮点FFT处理器具有较大资源开销的设计瓶颈,采用基于单口存储器的FIFO构建共享蝶形结构的R2/22SDF流水可配置结构.采用适合浮点设计的基2/22算法实现流水结构,不仅有利于可配置电路的实现,还能够有效减少复数乘法次数,提高复数乘法器的计算效率.采用双倍数据位宽的单口存储器实现FIFO存储器,有效避免了双口存储器面积和功耗较大的问题.改进的蝶形共享结构实现两级蝶形的合并,解决了单路径延迟反馈流水线结构蝶形单元利用率低的问题.与传统流水线结构FFT处理器设计相比,有效降低了浮点设计中的资源开销,提高了计算单元的利用效率.     

一种按时间抽取的混合基实序列高效FFT算法

针对2N点实序列FFT的实现,分析了FFT运算的基本原理,并在基本原理的基础上介绍了一种按时间抽取的混合基FFT算法.此算法采用"包装"算法和基2-基4混合算法结合的方法进行运算.通过复杂度分析,显示了此算法与传统的单一基2或基4的FFT相比,大大减少了计算过程中所需的实加法的个数;当点数大于1024时,所需实乘法的个数也有所减少.这是一种实序列FFT的高效低复杂度算法.     

超长可变点数FFT处理器设计与实现

介绍了超长可变点数序列FFT处理器的实现方法。采取将一维大点数FFT转换为二维小点数子FFT处理的措施,减小了存储器规模。使用乒乓RAM将基本运算模块级联,形成流水线结构,可连续高速计算N点复数序列FFT/IFFT。用现场可编程门阵列(FPGA)实现了可计算1k~1M点序列长度可变的FFT/IFFT处理器。     

An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications

In this brief, a high-throughput and low-complexity fast Fourier transform (FFT) processor for wideband orthogonal frequency division multiplexing communication systems is presented. A new indexed-scaling method is proposed to reduce both the critical-path delay and hardware cost by employing shorter wordlength. Together with the mixed-radix multipath delay feedback structure, the proposed FFT processor can achieve very high throughput with low hardware cost. From analysis, it is shown that the proposed indexed-scaling method can save at least 11% memory utilizations compared to other state-of-the-art scaling algorithms. Also, a test chip of a 1.2 Gsample/s 2048-point FFT processor has been designed using UMC 90-nm 1P9M process with a core area of 0.97 mm². The signal-to-quantization-noise ratio (SQNR) performance of this test chip is over 32.7 dB to support 16-QAM modulation and the power consumption is about 117 mW at 300 MHz. Compared to the fixed-point FFT processors, about 26% area and 28% power can be saved under the same throughput and SQNR specifications.     

改进的任意基FFT整序算法

本文提出了一种改进的适合于任意基ＦＦＴ变换的整序算法,改进整序算法采用循环嵌套结构,减少了运算量,实验结果表明,改进整序算法的运算时间较其它整序算法少。     

An architecture for human-network interfaces

Some of the issues (and their consequences) that arise when human-network interfaces (HNIs) are viewed from the perspective of people who use and develop them are examined. Target attributes of HNI architecture are presented. A high-level architecture model that supports the attributes is discussed. A preliminary opportunity analysis that estimates the savings possible with the proposed model is provided