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分段线性取样鉴相频率合成器的混沌现象 总被引:2,自引:0,他引:2
本文从理论上分析了取样锁相式频率合成器混沌的产生机理和产生条件,探讨了奇异吸子的相空间轨迹及其演变规律,通过计算机模拟给出了以T为岔参数的分岔图和混沌区域随系统参数的变化曲线。 相似文献
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本文提出一种新的提高频率合成器鉴相频率的方法,它采用脉冲内插方式实现,整个电路简单,且容易实现。文中给出了实现框图和关键电路,并对其工作原理作了详细说明。 相似文献
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分析和研究取样鉴相数字合成器环中的混沌动力学行为,根据Ushio与Hira等人的方法,从理论上证明了当系统参数满足一定条件时,系统会出现分岔现象,并具体计算出系统在各个不动点处的Hopf分岔集、系统的李雅普诺夫指数以及豪斯道夫维数。通过对系统进行计算机模拟,观察到系统的奇异吸引子,奇异吸引子的自相似性,系统在混沌状态下对初始条件的灵敏依赖性,进一步证实了三角形取样鉴相数字合成器环中存在混沌现象。 相似文献
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简要说明了PE3236的特点,并结合具体实际的工程应用说明了应用PE3236设计频率合成器的具体方法。 相似文献
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对取样锁相频率合成器的工作原理、技术特点等进行了描述,着重分析了其低相噪、低杂散特性,讨论了环路滤波器与环路扩捕的设计对环路稳定性的贡献,最后给出了X频段取样锁相频率合成器的电技指标. 相似文献
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A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA cu... 相似文献
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一种应用于CMMB的双频段低噪声频率合成器 总被引:1,自引:1,他引:0
A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm2. 相似文献
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介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。 相似文献
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复杂频率源系统,其参考信号需要进行多路功分处理,该处理会对参考信号的相位噪声产生影响。文章针对参考信号功分放大带来的相位噪声恶化现象,给予了详细的理论分析,并结合实例,给出适合工程需要的解决方法,工程实践中验证了该方法的有效性。 相似文献
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首先介绍了锁相环的基本原理,再介绍一个集成VCO的宽带频率合成器芯片ADF4351,并用该芯片设计一个输出为154.8MHz~212.775MHz的频率合成器,实测其相位噪声和杂散指标都能很好满足设计要求,能满足多种通信系统对信号源的需求。 相似文献
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A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc. 相似文献
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在此介绍了小数分频锁相频率合成器的相关理论。设计一个带宽为580 MHz、杂散抑制度≤-60 d Bc、相位噪声≤-85 d Bc/Hz@10 k Hz的C频段宽带低杂散频率合成器。利用双环锁相频率合成技术和小数分频锁相技术,实现了宽带、低杂散的锁相频率合成器的设计。最后经过测试近端杂散指标≤-60 d Bc,远端杂散指标≤-70 d Bc,偏移10 k Hz的相位噪声为-89.95 d Bc/Hz,技术指标都优于设计要求。 相似文献
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为了研制一种锁定时间短、相位噪声低、杂散抑制度高的频率合成技术,采用了直接数字式频率合成器(DDS)驱动锁相环(PLL)的结构。该频率合成器综合了DDS频率转换速度快、频率分辨率高和PLL输出频带宽、输出杂散低的优点。基于该结构研制实现了输出频率范围为700~800 MHz的宽带频率合成器,实验结果表明该频率合成器扫描模式Δf=1 MHz锁定时间不超过20μs,跳频模式Δf=50 MHz的定时间不超过30μs,近端杂散抑制度优于-50 dBc。 相似文献
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This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receivers.Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition,a fully-differential charge pump is presented.An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented.Test results show that the RMS phase error is less than 0.7°in integer-N mode and less than 1°in fractional-N mode.The... 相似文献