Anomalous junction leakage current induced by STI dislocations andits impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction     

The effect of oxide charges at LOCOS isolation edges on oxidebreakdown

The degradation of time dependent dielectric breakdown (TDDB) characteristics at LOCOS isolation edges has been studied using MOS capacitors with and without field oxide edges under gate electrodes. The wear-out mode was shifted toward shorter breakdown time by field oxide etching right after the conventional LOCOS process. An increase in leakage current was observed at the isolation edge, so that the current enhancement is regarded as one of the main causes of the degradation. The current was reduced by constant current stress, suggesting the neutralization of positive charges due to electron trapping. The authors attribute the current enhancement causing the degradation to the buildup of positive charges at the isolation edges. Carrier injection before TDDB tests was found to improve the degradation of the wear-out mode     

A leakage current mechanism caused by the interaction of residualoxidation stress and high-energy ion implantation impact in advancedCMOS technology

In this paper, we report abnormal junction leakage current characteristics in sub-quarter micron CMOS formed by OSELO-II isolation method and high-energy ion implantation for well formation. The phenomena have not been found in other isolation schemes such as single Si₃N₄ spacer OSELO (SSS-OSELO), modified conventional LOCOS (MLOCOS) and shallow trench isolation (STI). From the defect analysis and process simulation based on the actual recipe, the abnormal leakage is found to be generated from the lattice defects at the edge of field oxide and caused by the combination of oxidation stress, and high-energy ion implantation. A process condition in the high-energy ion implantation and isolation process is proposed to reduce the leakage current     

一种基于刻蚀的SOI深槽介质隔离工艺

介绍了一种基于刻蚀的SOI深槽介质隔离(DTI)工艺。该工艺采用BOSCH刻蚀、兆声清洗、多晶硅回填、刻蚀平坦化等技术,制作流程简单。其介质隔离击穿电压可以根据电路的需要进行调整,并可根据氧化层厚度进行预测。其介质隔离漏电流极低。     

Analysis of band-to-band tunneling leakage current intrench-capacitor DRAM cells

Evidence demonstrating that the band-to-band tunneling leakage current occurs mainly at the edge of the self-aligned isolation rather than the trench upper corners is presented. Moreover, the leakage current increases drastically with the decrease of capacitor oxide thickness. It is shown that the leakage current limits the thickness of capacitor oxide to more than 80 Å even if the operation voltage is reduced to 3.3 V from 5 V     

A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

A (dynamic random-access memory) DRAM cell using a trench capacitor with a grounded substrate plate has been demonstrated, fabricated of functional fully decoded 64K arrays. The cell array is located inside the well and the trench capacitor extends from the planar surface through the well and epitaxial layer into the heavily doped substrate. The polysilicon inside the trench, connected to the source region of the transfer device, is used as the storage node and the bulk silicon surrounding the trench serves as the capacitor plate electrode. The cell features small area, high capacitance, small leakage current, low soft error rate, reduced surface topography, and a very stable capacitor-plate electrode. The arrays were fabricated in an advanced, 3.3-V, n-well epitaxial CMOS technology with a 15-nm gate insulator. The n- and p-channel transistors, exhibit transconductances of 120 and 650 mS/mm, respectively, at effective channel lengths of 6.0 /spl mu/m. Ring oscillators designed at this length have delays of 170 ps at 3.3 V.     

Reduction of leakage current at the gate edge of SDB SOI NMOStransistor

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, ~2500 Å) and fully depleted (FD, ~800 Å) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES IIb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to ~pA and no hump was seen on the drain current curve     

On the retention time distribution of dynamic random access memory(DRAM)

The retention time distribution of high-density dynamic random access memory (DRAM) has been investigated. The key issue for controlling the retention time distribution has been clarified and its model has been proposed for the first time. Trench capacitor cell with 0.6-μm ground rule was evaluated. It was found that the retention time distribution consists of “tail distribution” and “main distribution.” “tail distribution,” by which DRAM refresh characteristics are restricted, depends on the boron concentration of the memory cell region. As boron concentration of the memory cell region increases, “tail distribution” is enhanced. This enhancement is due to the increase of the junction leakage current from the storage node. For the purpose of accounting for the nature of “Tail Distribution,” the concept of thermionic field emission (TFE) current has been introduced. The high electric field at pn junction of the storage node enhances thermionic field emission from a deep level. The activation energy of the deep level is normally distributed among the memory cells, which leads to the normal distribution of log(retention time). Two methods for reducing “tail distribution” are proposed. One is to reduce the electric field of the depletion layer of the storage node. The other is to reduce the concentration of the deep level for TFE current     

Junction leakage characteristics in modified LOCOS isolationstructures with a nitride spacer

Junction leakage characteristics in modified local oxidation of silicon (LOCOS) isolation structures have been studied when a nitride spacer was used to prevent bird's beak encroachment. Junction leakages with very low activation energy and strong voltage dependence were observed in the nitride spacered LOCOS. Comparative studies on the junction leakages of nonrecessed and recessed LOCOS have revealed that an additional silicon recess process after nitride spacer formation reduces the junction leakage current     

Novel cell transistor using retractedSi3N4-liner STI for the improvement of dataretention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si₃N₄-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-μm technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si₃N₄-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-μm technology and beyond     

Trench capacitor leakage in high-density DRAM's

The leakage current between trench capacitors for megabit dynamic MOS memories has been modeled and studied through simulations. The minimum substrate doping density, to limit the leakage current to 1 pA/µm, has been determined as a function of trench-trench spacing. The effect of all other relevant parameters on the required substrate doping density has also been investigated. Furthermore, the substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has been estimated. It is found that, for trench spacing of 0.75 µm or more, one can always find an intermediate range of substrate doping concentrations for which both the trench-trench leakage and the junction breakdown can be avoided.     

新型集成电路隔离技术——STI隔离

集成电路器件的特征尺寸进入深亚微米时代后,由于微细化和性能方面的影响,一些传统的器件结构将不再适用。传统的本征氧化隔离技术由于漏电流、平坦化、高温再分布等方面的原因,将被浅沟隔离技术所取代。论述了集成电路进入深亚微米时代后的STI(浅沟隔离)技术,指出了STI隔离工艺的主要特点、关键工艺及工艺实现方法。     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

双极RF功率管的深阱结终端

给出了双极 RF功率管新的深阱结终端结构 .模拟分析表明 ,具有优化宽度、优化深度且填充绝缘介质的深阱结终端结构能使雪崩击穿电压提高到理想值的 95 %以上 .实验结果表明 ,深阱结终端结构器件 DCT2 6 0的BVCBO为理想值的 94 % ,比传统终端结构器件高 14 % ;与传统结构相比 ,在不减小散热面积的情况下 ,该结构还减小集电结面积和漏电流 ,器件的截止频率提高 33% ,功率增益提高 1d B     

A study of stress-induced p/sup +//n salicided junction leakage failure and optimized process conditions for sub-0.15-/spl mu/m CMOS technology

We have clarified that mechanical stress combined with a shallower junction at the active edge is the main cause of junction leakage current failure of shallow p/sup +//n salicided junctions for sub-0.15-/spl mu/m CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of the narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p/sup +//n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge/sup +/ pre-amorphization in a narrow p+/n salicided junction.     

A new and improved borderless contact (BLC) structure forhigh-performance Ti-salicide in sub-quarter micron CMOS devices

We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO_x N_y film to act as the selective etching stop layer and the additional n⁺ and p⁺ source-drain double implant structure (DIS) are employed in the studied device. The additional n⁺ and p⁺ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

High-performance cell transistor design using metallic shieldembedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's

In this paper, the cell transistor design issues for the Gbit level DRAM's with the isolation pitch of less than 0.2 μm caused by the inverse-narrow-channel effect (INCE) and the neighboring storage-node E-field penetration effect (NSPE) will be discussed. Then we propose novel DRAM cell transistor structure by employing metallic shield inside the shallow trench isolation (STI). As confirmed by three-dimensional (3-D) device simulation results, by suppressing the inverse narrow-channel effect and the neighboring storage-node E-field penetration effect using metallic shield inside STI, we can obtain reliable cell transistors with low-doped substrate, low junction leakage current and uniform V_TH a distribution regardless of the active width variation     

Depletion trench capacitor technology for megabit level MOS dRAM

A new technology has been developed for future megabit level MOS dRAM's, in which a depletion-type capacitor is formed at a trench in the cell capacitor region. Trenches have been successfully formed by reactive ion etching utilizing CBrF3gas at a pressure of about 14 mTorr. Phosphorous could be doped onto the trench surface with sufficient controllability using a phospho-silicate glass film as a diffusion source. The capacitance of the depletion trench capacitor (DTC) was influenced by the surface orientation of the trench sidewalls. DTC breakdown voltage where gate oxide thickness was 20 nm was more than 7 V. This is large enough for practical use under 3-V operating conditions.