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1.
介绍了应用高速DSP芯片TM320LF2407A开发的具有RS-485网络通讯功能的高性能通用变频器,并对其硬件,通讯协议,变频器DSP软件及其监控计算机软件作了介绍。  相似文献   

2.
本文介绍了同频直放站的工作原理,并以Comba公司RS-2110B载波选频直放站为例,详细阐述了入网测试中,直放站的带外抑制参数的具体测试方法。  相似文献   

3.
严琴  冯勇建 《传感技术学报》2007,20(6):1303-1306
在无线通信中使用跳频技术是军事通信中最主要的抗干扰手段之一,而如果系统中使用合适的中心频率可以快速跟踪跳频变化的带通滤波器将可以明显改善系统的抗干扰性能.介绍了一种用硅玻璃键合工艺制作的微型梁式可变电容器,设计并制作了由MEMS工艺实现的微型的静电驱动的可变电容器件,用这种方法制作的电容器件具有良好的线性、较小的滞后和稳定的工作特性.设计了可用于15~50 kHz跳频应用的带通滤波器,可达到连续选频的目的.  相似文献   

4.
研究卫星天线射频信号优化问题,因镜频干扰在变频接收系统中影响很大,通常采用高品质的镜像抑制带通滤波器来处理高频信号.为了提高带通滤波器的镜像信号抑制能力和减小噪声系数,进一步减小多种干扰,提出微带带通滤波器设计方法和ADS软件优化设计高镜像抑制方法.方法通过对传输零点的准确定位,可实现选择性地抑制镜像信号.理论分析和仿真结果表明,所设计的带通滤波器性能和理论值一致,具有高镜像抑制能力、噪声系数低,同时还可以满足带内插损和带外抑制的设计要求,对工程应用有一定的指导意义.  相似文献   

5.
讨论通用变频器的电磁干扰及其对电气设备的影响,介绍抑制电磁干扰的方法。  相似文献   

6.
张友俊  杨希 《计算机仿真》2021,38(2):145-148,154
在现今复杂的通信环境之下,人们对着通信的质量也有着不断上升的需求,通信领域之中也不断涌现新的协议理论,而在这些新的协议则需要不断地更新相应的硬件支持,同时也对收发端滤波的使用灵活性等性能有了更高的要求.针对上述条件,使用可电调和开关可切换的结构,在ADS中仿真设计了一款带宽切换后保持不变且频率可调的带通滤波器.其带宽范...  相似文献   

7.
利用电磁兼容设计方法通过对特性阻抗、微孔、布局布线、电源模块、接地等技术的研究.进行了GPS上变频器的设计.实验测试结果证明,其输出信号抗噪声能力比没有经过电磁兼容设计产品高15 dB,从而使产品更具有可靠性.  相似文献   

8.
文章结合卫星通信用L波段上变频器的方案,给出了选择滤波器应考虑的因素,并介绍了微带交指滤波器和发夹线滤波器特性以及设计方法。  相似文献   

9.
提出了一种基于LTCC级联技术的边带陡峭高阻带抑制多级带通滤波器的实现方法。该滤波器电路由两个谐振部分级联而成,每个部分均由电感耦合的四阶谐振腔组成。在一般抽头式梳状线滤波器设计的基础上,引入了交叉耦合,形成传输零点,并结合电路仿真以及三维电磁场仿真,辅之以DOE(Design Of Experiment)的设计方法,设计出一种尺寸小、频率选择性好、边带陡峭、阻带抑制高的滤波器。实际测试结果与仿真结果吻合较好,中心频率为3.25 GHz,其1 d B带宽为300 MHz,在1 GHz2.86 GHz频率上的衰减均优于60 d B,在3.64 GHz2.86 GHz频率上的衰减均优于60 d B,在3.64 GHz3.84 GHz频率上的衰减均优于80 d B,在4.08 GHz3.84 GHz频率上的衰减均优于80 d B,在4.08 GHz5.8GHz频率上的衰减均优于60 d B,体积仅为6.1 mm×2.5 mm×1.5 mm。  相似文献   

10.
双音多频接收系统分析及其FPGA设计   总被引:1,自引:0,他引:1  
本文分析了在通信系统有着广泛应用的双音多频DTMF(DUAL TONE MULTI FREQUENCY)并设计了针对DTMF信号的接收及判别系统。系统根据ITU-T Q.24要求,能够正确的接收和判读输入信号。整个设计采用了有限冲击相应FIR滤波器完成对DTMF输入信号的滤波,保证了滤波输出信号的线性相位,同时采用非相干过零检测电路进行检测,易于数字电路实现,并利用现场可编程门阵列实现了整个设计,使整个电路结构合理,实现简单。  相似文献   

11.
An important problem in designing RFIC in CMOS technology is the parasitic elements of passive and active devices that complicate design calculations. This article presents three LNA topologies including cascode, folded cascade, and differential cascode and then introduces image rejection filters for low‐side and high‐side injection. Then, a new method for design and optimization of the circuits based on a Pareto‐based multiobjective genetic algorithm is proposed. A set of optimum device values and dimensions that best match design specifications are obtained. The optimization method is layout aware, parasitic aware, and simulation based. Circuit simulations are carried out based on TSMC 0.18 μm CMOS technology by using Hspice. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.  相似文献   

12.
In this paper, a novel design method for reconfigurable bandpass filter (BPF) with constant absolute bandwidth (ABW) based on neural network is proposed. A lumped-element circuit is used to design the reconfigurable BPF, which consists five series LC tanks. Three series tanks can provide three transmission poles, while two parallel tanks can introduce two same transmission zeros (TZs). This method allows designing BPFs with tunable center frequency and constant ABW. A set of inductance and capacitance values for the center frequency and ABW requirements are optimized by using neural network. Then, optimize the capacitance values to adjust the center frequency with fixed inductance values by the three series tanks and the TZ by the parallel tanks. In order to verify this design method, three varactor diodes are employed to achieve the reconfigurable BPFs with the constant ABW under different work states. Experiments show that this method can optimize multiple LC circuit parameters of BPFs, which meet design requirements, with the same ABW and different center frequencies effectively and accurately  相似文献   

13.
This article presents two new types of tunable filters with constant absolute bandwidth using varactor‐loaded microstrip resonators. First, the second‐ and third‐order Butterworth tunable filters are designed based on the parallel coupled‐line J inverters. Second, a fourth‐order Chebyshev tunable filter is designed based on the alternative J/K inverters, in this design, two adjacent resonators are coupled with each other through a short‐circuited transmission line as the K inverter. The proposed two topologies can be easily extended to high‐order tunable filter. Three tunable bandpass filters with J and alternative J/K inverters, respectively, are built with a tuning range from ~1.8 to ~2.3 GHz. The measured second‐order filter has a 3‐dB bandwidth of 160 ± 6 MHz and an insertion loss of 2.4–3.8 dB. The third‐order filter shows a 3‐dB bandwidth of 197 ± 5 MHz and an insertion loss of 3.8–4.8 dB. The fourth‐order filter shows a 3‐dB bandwidth of 440 ± 5 MHz and an insertion loss of 2.1–2.6 dB. For all the designed filters, the measured results are found in excellent agreement with the predicted and simulated results. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:681–689, 2014.  相似文献   

14.
This letter presents a tunable bandpass filter (BPF) with wide tuning range of center frequency and high selectivity. The wide frequency tuning range is achieved by two pairs of switchable varactors‐tuned parallel coupled line resonators with direct‐feed structure, which can be switched to lower and higher frequency resonator modes by using p‐i‐n diodes. Since the electromagnetic mixed coupling and frequency‐variant source‐load coupling are incorporated in this configuration, three self‐adaptive transmission zeros (TZs) close to the tunable passband are obtained. Also, three TZs can almost keep the same relative location of passband to achieve continuous high selectivity and good out‐of‐band rejection over the whole frequency tuning range. Meanwhile, by selecting a proper coupling region, a constant fractional bandwidth (CFBW) in the frequency tuning process can be realized. For verification, a tunable 0.86‐3.83 GHz BPF with a 12% CFBW and high selectivity is designed, fabricated and measured. The experimental results show the proposed filter has the advantages of wide tuning range and high selectivity.  相似文献   

15.
Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.
Lounis KessalEmail:
  相似文献   

16.
This study presents a wideband bandpass filter (WBBPF) with wide and high stopband suppression by loading a stepped‐impedance resonator (SIR). The prototype of WBBPF is composed of an inverted π‐shaped resonator with T‐shaped resonator and open stub loaded, centrally. Odd‐/even‐mode analysis technique is employed to characterize the resonant properties of this prototype. Then, a SIR is loaded to this filter, asymmetrically, to improve the out‐of‐band performance. For experimental validation, a WBBPF is designed, fabricated, and tested. The measurement results show that the center frequency of WBBPF is located at 5.095 GHz, and the 3‐dB fraction bandwidth is about 71%. Plus, the out‐of‐band suppression with 30‐dB rejection level can be extended to 18.17 GHz.  相似文献   

17.
为解决采样过程中因有用信号混叠导致多频段信号在同一平台上无法正常接收的问题,提出一种基于二阶带通采样的抗混叠滤波算法。多频段带通信号通过可调延时差的二阶带通采样处理,形成两路具有相位差的采样后信号,利用相位差设计抗混叠滤波器,调整两信号相位,使其中一个信号经过叠加后信号为零,而另一信号不变,实现两混叠信号的分离。仿真结果表明,该抗混叠滤波算法可以有效实现两路混叠信号的分离且信号具有较好的重构性能。  相似文献   

18.
自抗扰控制是我国著名学者韩京清原创的先进控制技术,本文针对自抗扰控制(ADRC)在高阶系统应用中控制器设计和参数整定问题,提出了串级自抗扰控制(CADRC). CADRC把高阶被控对象分解为含确定性部分和含总扰动的低阶部分的串联组合,采用由内环和外环组成的串级控制系统来完成控制.该CADRC方案的内环采用内模控制,外环采用经典ADRC.外环ADRC的被控对象是一个等效的低阶系统,可以采用带宽法进行整定,而内环的内模控制采用高阶低通滤波器进行回路成形设计和参数整定.仿真研究表明,所提出的方法是有效的,具有良好的工程应用前景.  相似文献   

19.
In this article, the design and test of both a K‐band dual‐mode bandpass filter (BPF) pair and a K‐band triple‐mode BPF are presented based on N‐mode temporal coupled‐mode theory (CMT). The expressions of transmission and reflection responses are analytically derived. All the parameters in the expressions have clear physical meanings and are easily optimized to reach the required filter performance. Aided by eigenmode simulations, concrete structures of the three integrated BPFs are designed and optimized to approach the calculated physical parameters. After the fabrications and measurements of the three BPFs, extended upper/lower stopband with high stopband rejections are achieved, and by increasing the number of resonant modes, improved frequency selectivity and better passband flatness are obtained. The analytical analysis well predicts the simulation and measurement results, which provides an efficient way for BPF designs. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:609–622, 2016.  相似文献   

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