平面双栅型离子栅晶体管的逻辑功能研究

离子栅晶体管作为一种新型半导体器件,因其低电压、可多栅调控的特点以及在化学传感和类脑器件方面的运用而备受关注。由于离子栅具有侧向长程调控的能力,十分有利于制备成平面双栅的结构,进一步利用两个栅极输入对离子与沟道内电子耦合情况的调控,可以实现独特的逻辑输出。为了更好地实现该功能,采用射频磁控溅射制备了铟镓锌氧(IGZO)沟道和铟锌氧(IZO)电极,以聚电解质材料——聚苯乙烯磺酸钠(PSSNa)作为离子栅介质制备了平面双栅型离子栅晶体管。在测量其晶体管基本电学特性的基础上,通过对双栅调控机制的研究,首先实现了与逻辑(AND)的输出,再利用负载电阻后反相器的非门(NOT)作用,将两者结合,形成与非逻辑(NAND)输出,从而证明离子栅晶体管在平面双栅结构下仅需简单的器件和电路就能实现多种基本逻辑功能。     

KH550-GO复合栅介质低压氧化物薄膜晶体管

采用旋涂法制备硅烷偶联剂-氧化石墨烯(KH550-GO)新型复合栅介质薄膜,由于栅介质层和沟道层界面处明显的双电层效应,单位面积电容高达2.18×10~(–6)F/cm~2。通过自组装法,借助磁控溅射仪,仅需一次掩膜,即可同时生成晶体管的沟道与源漏电极。利用半导体参数分析仪在室温黑暗的条件下测量该晶体管的电学特性,结果表明,KH550-GO栅介质氧化物薄膜晶体管具有优良的电学性能,其工作电压仅为2 V、饱和电流为580μA、亚阈值摆幅108 m V/dec、开关比4×10~7、场效应迁移率16.7 cm~2·V~(-1)·s~(-1)。     

双栅酞菁铜有机薄膜晶体管

有机薄膜晶体管以其成本低、柔性好、易加工等优点越来越受到人们的青睐,目前已广泛应用于低端器件。为了获得更实际的应用,OTFTs的性能还需进一步的提高和改善。文章中以酞菁铜(CuPc)为有机半导体材料,制备了双栅结构的有机薄膜晶体管,其阈值电压为-4.5V,场效应迁移率0.025cm2/V.s,开关电流比Ion/Ioff达到9.8×103,与单栅有机薄膜晶体管相比,双栅器件在更低的操作电压下获得了更大的输出电流,场效应迁移率更高,而且通过对两个栅压的调节,对导电沟道实现了更好的控制,器件性能有了较大的提高。     

薄起始层的VHF PECVD底栅微晶硅薄膜晶体管

对微晶硅薄膜晶体管,尤其对底栅型晶体管,在衬底和晶化层间存在一层非晶相起始层,这将严重影响器件性能.文中采用降低硅烷浓度的方法简便有效地减薄了用超高频化学气相法直接沉积的微晶硅薄膜起始层的厚度,得到起始层厚度小于20nm的微晶硅薄膜.在硅烷浓度为2%的条件下采用四版工艺制备了具有Al/SiNx/μc-Si/n+-μc-Si/Al结构的底栅微晶硅TFT,其开关比(Ion/Ioff)达到106,场效应迁移率为0.7cm2/(V·s),阈值电压为5V左右.     

多晶硅薄膜晶体管的栅电容模型

多晶硅薄膜晶体管具有独特的栅电容特性,即泄漏区中栅源电容的反常增大和饱和区中栅漏电容由于kink效应的增大.基于Meyer模型,考虑了泄漏产生效应和kink效应,对多晶硅薄膜晶体管的栅漏电容和栅源电容特性进行了建模研究.对实验数据进行拟合发现,提出的模型与实验数据符合得较好,能准确地预测多晶硅薄膜晶体管的栅电容特性.     

非晶硅薄膜晶体管基于表面势的栅电容模型

基于Lambert W函数,推导出非晶硅薄膜晶体管表面势的解析解,并将其与泊松方程的数值解进行对比.结果显示:该求解大大提高了计算效率,且精确度极高.基于有效温度近似,并利用所求解到的表面势,建立器件的栅电容模型.该模型可连续、准确地描述a-Si:H TFT在所有工作区的动态特性.最后,将模型结果与实验数据进行了对比,两者拟合良好.     

底栅微晶硅薄膜晶体管

对底栅微晶硅TFT的微晶硅材料生长孵化层问题进行了详细讨论,发现低硅烷浓度是减薄该层厚度的有效途径.同时又发现,以SiNx为栅绝缘层的底栅TFT,对随后生长的硅基薄膜有促进晶化的作用(约20%).沉积底栅TFT的微晶硅有源层时,必须计入该影响.因此为了获得良好的I-V特性,选用的硅烷浓度不宜低于3%.由硅基薄膜晶化体积比与系列沉积工艺条件关系和TFT所得薄膜晶化体积比的对比,可清晰证实SiNx对晶化的促进作用.     

有机介质层铟锌氧化物薄膜晶体管

利用直流磁控溅射方法在玻璃基板上室温制备非晶铟锌氧化物半导体薄膜,薄膜表面平整。采用旋涂法室温制备聚四乙烯苯酚有机介质层。以铟锌氧化物薄膜作为沟道层、聚四乙烯苯酚作为介质层,成功制备了顶栅结构的薄膜晶体管。测试结果表明,所制备的薄膜晶体管具有饱和特性且为耗尽工作模式,薄膜晶体管的阈值电压为3.8V,迁移率为25.4cm2.V-1.s-1,开关比为106。     

基于表面势的多晶硅薄膜晶体管的栅电容模型

显式地推导多晶硅薄膜晶体管(Polysilicon thin-film transistors,poly-SiTFT)表面势隐含方程的近似解,该求解法非迭代的计算大大地提高了计算效率,且精确度非常高,与数值迭代结果比较,绝对误差范围只在纳伏数量级。利用求得的表面势,建立了一个poly-SiTFT栅电容模型,该电容电压模型能连续、准确地描述poly-SiTFT在线性区和饱和区的动态特性,同时该模型考虑了kink效应、沟道长度调制效应和寄生电容等。对实验数据进行拟合发现,提出的模型与实验数据符合得较好,能准确地预测poly-SiTFT的栅电容特性。     

高性能双栅复合介质ZnO薄膜晶体管的模拟

提出ZnO薄膜晶体管的一种新型结构——双栅复合介质结构,并利用ATLAS软件对双栅复合介质结构与双栅单介质结构进行仿真。对比分析结果表明,采用复合介质材料可以明显提高器件的电学特性,在相同偏置条件下,双栅复合介质结构饱和电流为5.5×10-5 A,阈值电压为5.83V,亚阈值斜率为0.128V/dec,开关电流比为109;双栅单介质结构相应值分别为1.3×10-7 A、15.5V、0.297V/dec和108。通过晶界势垒高度随VGS变化分析了新型结构阈值电压降低的物理机制。     

Starch as ion-based gate dielectric for oxide thin film transistors

Application of nature bio-materials in electronics represents an emerging field of science and technology that began a few years ago. For the dielectric of transistors, the ion-based electric double layer (EDL) gating has becoming the widely accepted theory of charge modulation with hydrated bio-polymer dielectrics. Herein, we report on the use of starch as the ion-based gate dielectric for oxide thin film transistors. Two types of starches, i.e., water-soluble starch and potato starch were studied either with or without the incorporation of glycerol. Important parameters including mechanical strength, surface morphology, specific capacitance and ion conductivity were analyzed in accordance with the molecular structure of starches. The transistor performance was found in close relation with the specific capacitance and ion conductivity of the starch dielectrics. Higher on/off ratio (2.6 × 10⁶) and field mobility (0.83 cm²V⁻¹s⁻¹) were obtained with glycerol incorporated potato starch due to the advantage in capacitance and ion conductivity. Lower ion conductivity of the water-soluble starch on the other hand caused the large current hysteresis, so the current retention property was examined for the potential application as a memory element. Collectively, this work solidifies our knowledge on the material type, EDL gating mechanism and applicability of nature bio-material gated transistors.     

Oxide-based thin film transistors for flexible electronics

The continuous progress in thin film materials and devices has greatly promoted the development in the field of flexible electronics.As one of the most common thin film devices,thin film transistors (TFTs) are significant building blocks for flexible platforms.Flexible oxide-based TFTs are well compatible with flexible electronic systems due to low process temperature,high carrier mobility,and good uniformity.The present article is a review of the recent progress and major trends in the field of flexible oxide-based thin film transistors.First,an introduction of flexible electronics and flexible oxide-based thin film transistors is given.Next,we introduce oxide semiconductor materials and various flexible oxide-based TFTs classified by substrate materials including polymer plastics,paper sheets,metal foils,and flexible thin glass.Afterwards,applications of flexible oxide-based TFTs including bendable sensors,memories,circuits,and displays are presented.Finally,we give conclusions and a prospect for possible development trends.     

Photocurable propyl-cinnamate-functionalized polyhedral oligomeric silsesquioxane as a gate dielectric for organic thin film transistors

A polyhedral oligomeric silsesquioxane (POSS)-based insulating material with photocurable propyl-cinnamate groups (POSS-CYNNAM) was designed and synthesized through simple single step reaction for use as a gate dielectric in organic thin-film transistors (OTFT). POSS-CYNNAM was soluble in common organic solvents and formed a smooth thin film after spin-casting. A thin film of POSS-CYNNAM was cross-linked and completely solidified under UV irradiation without the use of additives such as photoacid generators or photoradical initiators. ITO/insulator/Au devices were fabricated and characterized to measure the dielectric properties of POSS-CYNNAM thin films, such as leakage current and capacitance. A pentacene-based OTFT using the synthesized insulator as the gate dielectric layer was fabricated on the transparent indium tin oxide (ITO) electrode, and its performance was compared to OTFTs using thermally cross-linked poly(vinyl phenol) (PVP) as the insulator. The fabricated POSS-CYNNAM OTFT showed a comparable performance to devices based on the PVP insulator with 0.1 cm²/Vs of the field effect mobility and 4.2 × 10⁵ of an on/off ratio.     

Solution processable bilayered gate dielectric towards flexible organic thin film transistors

In this study, we have successfully explored the potential of a new bilayer gate dielectric material, composed of Polystyrene (PS), Pluronic P123 Block Copolymer Surfactant (P123) composite thin film and Polyacrylonitrile (PAN) through fabrication of metal insulator metal (MIM) capacitor devices and organic thin film transistors (OTFTs). The conditions for fabrication of PAN and PS-P123 as a bilayer dielectric material are optimized before employing it further as a gate dielectric in OTFTs. Simple solution processable techniques are applied to deposit PAN and PS-P123 as a bilayer dielectric layer on Polyimide (PI) substrates. Contact angle study is further performed to explore the surface property of this bilayer polymer gate dielectric material. This new bilayer dielectric having a k value of 3.7 intermediate to that of PS-P123 composite thin film dielectric (k ∼ 2.8) and PAN dielectric (k ∼ 5.5) has successfully acted as a buffer layer by preventing the direct contact between the organic semiconducting layer and high k PAN dielectric. The OTFT devices based on α,ω-dihexylquaterthiophene (DH4T) incorporated with this bilayer dielectric, has demonstrated a hole mobility of 1.37 × 10⁻² and on/off current ratio of 10³ which is one of the good values as reported before. Several bending conditions are applied, to explore the charge carrier hopping mechanism involved in deterioration of electrical properties of these OTFTs. Additionally, the electrical performance of OTFTs, which are exposed to open atmosphere for five days, can be interestingly recovered by means of re-baking them respectively at 90 °C.     

Low-voltage organic thin film transistors with hydrophobic aluminum nitride film as gate insulator

This paper reports on the low-voltage (<5 V) pentacene-based organic thin film transistors (OTFTs) with a hydrophobic aluminum nitride (AlN) gate-dielectric. In this work, a thin (about 50 nm), smooth (roughness about 0.18 nm) and low-leakage AlN gate dielectric is obtained and characterized. The AlN film is hydrophobic and the surface free energy is similar to the organic or the polymer films. The demonstrated AlN–OTFTs were operated at a low-voltage (3–5 V). A low-threshold voltage (−2 V) and an extremely low-subthreshold swing (∼170 mV/dec) were also obtained. Under low-voltage operating conditions, the on/off current ratio exceeded 10⁶, and the field effect mobility was mobility was 1.67 cm²/V s.     

Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd2O3 as gate dielectric

The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd₂O₃ has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 μm. The thin film transistors exhibit a high mobility of 4.3 cm² V^?1 s^?1 and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10⁵. The TFTs also exhibit good transconductance and gain band-width product of 1.15 × 10^?3 mho and 71 kHz respectively.     

Pentacene bottom-contact thin film transistors with solution-processed BZT gate dielectrics

The solution-processed high-k barium zirconate titanate (BZT) as gate dielectrics for bottom-gate pentacene-based organic thin film transistor (OTFT) applications is presented. To reduce the transistor threshold voltage, higher work function metals (Au) is used as the gate electrodes. The threshold voltage is efficiently decreased from −3.6 to −2.15 V as compared to that of Al. In addition, the UV/ozone was employed to treat the Au (source/drain) surface to improve the poor crystalline of pentacene grown on Au. Moreover, the surface morphologies and orientations of pentacene films were analyzed through atomic force microscopy (AFM) and X-ray diffraction. As the results, the stack of pentacene molecules from disorder state changed to vertical growth on the Au surface. Finally, the electrical properties of pentacene-based thin film transistors exhibit high field-effect mobility of 4.5 cm²/V·s, low subthreshold swing of 260 mV/decade, high on/off ratio of 1.4 × 10⁵ and low operation voltage of −5 V. These results are better than the reported data using bottom contact pentacene OTFTs.     

Top gate pentacene thin film transistor with spin-coated dielectric

Fabrication of top gate pentacene thin film transistor (TFT) is made possible with spin-coatable dielectrics by the technique presented here. Such fabrication has been impractical because of the ill effects a solvent can have on pentacene. A bilayer of pentacene on insulator that are coated on a mold is transferred to a glass substrate on which source and drain electrodes are defined. In the transfer process, pentacene is automatically patterned. This fabrication method allows for the channel length to be as small as photolithography would permit.     

Effects of vapor-annealed gate dielectric on the properties of zinc tin oxide transparent thin film transistors

We investigated the effects of vapor-annealed gate dielectrics on the mobility, threshold voltage, and other characteristics of bottom gate zinc tin oxide (ZTO) transparent thin film transistors (TTFTs). Here, Al₂O₃ films coated on dry oxidized Si wafers were annealed in a water vapor atmosphere before ZTO deposition and used as TTFT gate dielectrics. The vapor-annealed ZTO TTFTs exhibited 50% higher mobility than those that were not vapor annealed. This improvement in mobility is ascribed to the hydrogen passivation in the amorphous ZTO films     

A new biodegradable gate dielectric material based on keratin protein for organic thin film transistors

By virtue of the biocompatibility, environmental benignity, and sustainability, as well as low cost of keratin protein's source herein, we report its application as a gate dielectric material for organic electronic devices. Keratin protein, which is a biodegradable material was directly extracted from poultry chicken feathers (CFs). Solution-processed regioregular poly(3-hexylthiophene) (P3HT) organic thin film transistors (OTFTs) with keratin dielectric thin film exhibited enhanced charge mobility of 2.293 × 10⁻³ cm² V⁻¹ s⁻¹ (saturation regime), high on-off current ratio of 10⁵ and low threshold voltage, -1V as compared to conventional SiO₂ dielectric. All the fabrication processes were performed below 100 °C. A detailed semiconductor-dielectric interface study has revealed that the high content of β-sheet structure in keratin protein has guided the P3HT polymer chains, through supramolecular forces of interaction to form 2D nanoribbons of large crystallite size (150 nm) over keratin thin film. This has led to the reduced trapping sites at the semiconductor/dielectric interface and hence the enhanced electrical performance of OTFTs was observed. Atomic force microscopy (AFM) and Grazing Incidence X-ray diffraction (GI-XRD) study was further employed to explore the mechanism of formation of 2D nanoribbons of P3HT. The primary and secondary structure of keratin protein as analyzed by AFM, Transmission electron microscopy (TEM) and Fourier transform spectroscopy (FTIR) is also provided in this study. The water compatible nature of keratin has helped to overcome the common issue of dielectric layer washing that occurs mostly during fabrication of OTFTs by sol-gel method. The biodegradable nature of keratin protein has also been demonstrated here by providing it as feed to fishes in an aquarium.