Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.     

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.     

High-Speed and Low-Power GaAs Phase Frequency Comparator

A high-speed and low-power consumption phase frequency comparator (PFC) for a phase lock stable oscillator was designed and fabricated with a GaAs MESFET BFL circuit for the first time. The threshold voltage, gate width, and gate length of GaAs MESFET's in the PFC were determined by circuit simulations for a high-speed and low-power operation. The fabrication process used buried p-layer SAINT-FET's with 0.5-µm gate length. The fabricated PFC performed stable phase and frequency comparison up to 600 MHz at only 60 mW. Using dislocation-free wafers, the fabrication yield in the laboratory was more than 90 percent.     

A GaAs monolithic frequency divider using source coupled FET Logic

A GaAs monolithic binary frequency divider based on the new source coupled FET logic (SCFL) is reported. A very wide range for the threshold voltage in the constituent FET's is allowable because in principle the SCFL operates in a current mode. A single-clocked SCFL master-slave frequency divider was successfully fabricated with 1µm-gate MESFET's with a threshold voltage ranging from -0.7 V to +0.2 V. The highest operating frequency was 2.5 GHz at the power consumption of 25 mW.     

A 2Gb/s throughput GaAs digital time switch LSI using LSCFL

A GaAs four-channel digital time switch LSI with a 2.0-Gb/s throughput is developed. This switch consists of 4-bit shift registers, data latches, a counter, a control unit, and I/O buffer gates. The LSI includes 1176 devices (FET's, diodes, and resistors) and its equivalent gate number is 231 gates. Low Power Source Coupled FET Logic (LSCFL) operating in a true/complementary mode is used to ensure high-speed and low-power performance. MESFET's with 0.55-µm gate length are fabricated by the buried p-layer SAINT process, which satisfactorily suppresses short channel effects. Dislocation-free wafers are also used to provide high chip yields of 75 percent. The propagation delay time of the LSCFL basic circuit is 48 ps/gate with 1.4-mW/equivalent gate. The total power dissipation including input and output buffers is 0.64 W. The LSI speed performance is evaluated by measuring toggle frequency of the 1/4 frequency divider. The divider operates typically at 5.1 GHz, maximum 7.5 GHz. The newly developed high-speed digital time switch LSI makes possible time division switching services in TV and high-definition TV transmission systems.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.     

A gallium arsenide SDFL gate array with on-chip RAM

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAM's. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFET's with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.     

GaAs heterostructure FET frequency dividers fabricated with high-yield 0.5 mu m direct-write trilevel-gate-resist

Frequency dividers and FET test structures have been fabricated on selectively doped n/sup +/AlGaAs/GaAs heterostructure FETs (HFETs) with 0.5 mu m gate length electron-beam direct-writing on a novel trilevel resist, EBR-9/Ge/PMGI. A divide-by-two master-slave frequency divider fabricated with direct-coupled FET logic gates operated up to 9.3 GHz. The input frequency range of a divide-by-two transmission-gate frequency divider was from 3.2 to 12.2 GHz, with a supply voltage of 1.2 V at room temperature. The average propagation delay (fan-in and fan-out=1) was 18.2 ps/gate, with a power dissipation of 3.9 mW/stage. With a 3.5 mu m source-drain spacing, a peak transconductance of 360 mS/mm was measured. The functional yield of both discrete devices and circuits was 92% across 2 in-diameter wafers.<>     

GaAs MESFET ring oscillator on Si substrate

GaAs MESFET ring oscillators were fabricated on a Si substrate and successfully operated. Epitaxial techniques to grow a GaAs layer on a Si substrate were investigated. The device-quality GaAs epitaxial layer was obtained by introducing a Ge layer (by ionized cluster-beam deposition) and alternating GaAs/GaAIAs layers (by MOCVD). The typical transconductance of 140 mS/mm was obtained for the FET with a 0.5 µm × 10 µm gate. The minimum delay time was 66.5 ps/ gate at a power consumption of 2.3 mW/gate.     

Physical basis of short-channel MESFET operation II: Transient behavior

The large-signal switching behavior of planar short-channel metal-semiconductor field-effect transistors (MESFET's) is simulated numerically. First, the intrinsic response of the MESFET is simulated in two space dimensions and time, using measured electric-field-dependent drift velocities and diffusivities in the conventional semiconductor equations; results of the intrinsic device simulations are then used to study the circuit behavior of Si and GaAs MESFET's in two-input NOR circuits. Although the simulated 1-µm-gate Si and GaAs MESFET's have intrinsic response times of 11 and 9 ps to a gate pulse of - 2 V, for fan-in and fan-out = 2, the Si and GaAs NOR gates have average gates delays of 318 and 118 ps, respectively, for 1-µm gate lengths. The power-delay products for these 1-µm-gate Si and GaAs circuits are 1.8 and 1.5 pJ, respectively. These results are compared with measured data and their physical basis is discussed.     

Monolithic integration of Si MOSFET's and GaAs MESFET's

Integration of Si MOSFET's and GaAs MESFET's on a monolithic GaAs/Si (MGS) substrate has been demonstrated. The GaAs MESFET's have transconductance of 150 mS/mm for a gate length of 1 µm, and the Si MOSFET's have transconductance of 19 mS/mm for a gate length of 5 µm and an oxide thickness of 800 Å. These characteristics are comparable to those for devices fabricated on separate GaAs and Si substrates.     

High-speed frequency dividers with quasi-normally-off GaAs MESFETs

Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance obtained corresponds to a propagation delay of 145 ps for the constituent NOR-OR gates of fan-in/fan-out = 4/3, and it is made possible by careful optimisation of circuit design parameters.     

Ultra-High-Speed GaAs Monolithic Prescaler and Phase Frequency Comparator IC

A high-speed, low-power prescaler and phase frequency comparator (PFC) IC for a phase-lock stable oscillator was designed and fabricated on a single chip using GaAs MESFET BFL circuitry. The gate width of the master-slave T-type flip-flops used in designing the 1/32 frequency divider prescaler was determined by circuit simulations. The fabricated 1/32 prescaler operated up to 8.0 GHz while the fabricated monolithic prescaler and PFC IC performed stable division, and phase and frequency comparison at input frequencies up to 4.8 GHz with a chip power dissipation of only 715 mW.     

High-speed integrated logic with GaAs MESFET's

The feasibility of using GaAs metal-semiconductor field-effect transistors (GaAs MESFET's) in fast switching and high-speed digital integrated circuit applications is demonstrated. GaAs MESFET's with 1-/spl mu/m gate length are shown to have a current-gain-bandwidth product f/SUB T/ equal to 15 GHz. These devices exhibit a 15 ps internal delay in a large-signal switching test. A simple logic circuit consisting of MESFET's and Schottky diodes was monolithically integrated on a semiinsulating GaAs substrate. This logic circuit exhibits a propagation delay of 60 ps with no output load, and 105 ps when its output is loaded by three similar logic gates. A useful bandwidth of approximately 3 GHz is observed.     

A monolithic multigigabit/second DCFL GaAs decision circuit

A GaAs integrated circuit has been designed and fabricated to regenerate digital data at gigabit per second rates. The circuit architecture is direct-coupled FET logic (DCFL), and the fabrication is by self-aligned etched gate on CVD epitaxial material. The circuit includes a moderate-gain input amplifier with threshold adjustment, a clocked D flip-flop for data sampling and storage, and an output buffer for driving low impedance transmission lines. Dynamic performance measurements include correct regeneration of pseudorandom data at 2.0 Gbit/s, the maximum allowed by available instrumentation, and 1010... data at 2.4 Gbit/s. Rise/fall times below 150 ps into 50 Ω were observed. A minimum gate delay of 17.8 ps and a maximum toggle frequency of 3.8 GHz were measured with associated ring oscillator and binary frequency divider circuits, respectively.     

A 10-GHz frequency divider using selectively doped heterostructure transistors

We report the first complementary clocked frequency divider using dual gate selectively doped heterostructure transistors (SDHT's). The circuit employs a master-slave flip-flop design which consists of four direct coupled AND-NOR gates. The nominal gate length and the gate-gate, separation in the dual gate SDHT's are 1 µm. A maximum dividing frequency of 10.1 GHz at 77 K was achieved; at this frequency the circuit dissipated 49.9 mW at 1.67-V bias. This is the highest operating frequency reported for static frequency dividers at any temperature. At room temperature the dividers were operated successfully at frequencies up to 5.5 GHz with a total power dissipation of 34.8 mW at 1.97-V bias. The lowest speed-power product at room temperature was obtained at 5 GHz with 14.9-mW power dissipation at 1.45-V bias.     

Quasi-normally-off MESFET logic for high-performance GaAs IC's

The stringent pinchoff voltage control required by the normally-off GaAs FET logic approach appears to be a very serious limitation to its LSI capability. This paper presents the operation and performance of a more tolerant logic IC approach intented to succeed in manufacturing high-performance digital GaAs IC's with LSI complexities. The so-called "quasi-normally-off" MESFET's are utilized, i.e., transistors operating as enhancement-mode devices but having a pinch-off voltage indifferently positive or negative (-0.3 to +0.2 V typically). As well as the genuine normally-off logic, quasi-normally-off digital IC's require a single power supply with a small voltage value (about +3 V). Six alternative circuit configurations, which exhibit different complexity-performance tradeoffs, have been studied by computer simulation. Furthermore, file performance capability of this logic was experimentally tested on 11-stage ring-oscillator circuits fabricated with 1 × 35 µm gate MESFET's. Minimum propagation delays in the range 95-135 ps (depending on the logic gate configuration) and speed-power products of 200-250 fJ (atV_{DD} = 2.5V) were achieved. From these results, propagation times in the range 100-200 ps and figures of merit of 50-200 fJ can be expected for logic gates with 10-20-µm FET geometry and LSI-circuit fan-in/loading conditions.     

Improvement in threshold-voltage uniformity in submicrometer GaAs MESFET's using an implanted p layer

A significant improvement in threshold-voltage uniformity for submicrometer gate GaAs MESFET's fabricated by direct Si implan, tation was observed using an optimized p-buried layer on conventional undoped LEC-grown substrates. Using an optimized Be-implantation scheme, we have achieved standard deviations of the threshold voltage as low as 7.6 mV from 13 × 13 FET arrays and only 16.8 mV across a 3-in wafer for FET's with a gate length of 0.6 µm. This is a very promising result for extending the GaAs MESFET IC technology into VLSI circuit complexity.     

A high-transconductance self-aligned GaAs MESFET fabricated by through-AIN implantation

This paper describes a new technique for the fabrication of high-transconductance GaAs MESFET's. Tungsten-silicide gate, self-aligned GaAs MESFET's were fabricated on extremely thin channel layers formed by implantation through AlN layers on semi-insulating GaAs substrates. Transconductance of the through-implanted MESFET's showed 30- to 50-percent increase as compared with that of conventional self-aligned MESFET's and reached its maximum value at 300 mS/mm for 1-µm gate-length FET's. The uniformity of the threshold voltage across a 2-in wafer was also excellent with a standard deviation of 44 mV. Circuit simulation indicates that the advantage of these FET's becomes more crucial when used in a very large-scale integrated circuit (VLSI).