基于梯度方向算子的H.264帧内模式选择算法

提出梯度方向算子的概念,基于该算子提出了一种H.264帧内模式快速选择算法。本文首先应用梯度方向算子计算编码宏块中各4×4亮度子块的纹理特征和灰度起伏特征,根据这两种特征参量削减4×4帧内候选预测模式。通过统计宏块中各子块的4×4候选预测模式信息,结合梯度方向强度门限判别法削减宏块的16×16候选预测模式,通过率失真优化算法计算得到最优亮度预测模式。进一步根据亮度宏块和色度宏块的对应关系,在亮度候选预测模式的基础上对色度宏块候选预测模式进行削减,最后计算得到最优色度预测模式。该算法削减了50%以上的帧内预测模式,减少了帧内预测模式选择的运算量,实验表明,该算法能够在峰值信噪比和码流比特率变化轻微的前提下减少50%以上的运算量。      

H.264/AVC帧内4×4预测算法的高效流水线结构

H.264编码器中的帧内4×4预测部分具有严重的数据依赖性,它的硬件化设计很难采用流水线实现,从而导致关键路径很长,硬件利用率很低,成为H.264编码器设计中的一个瓶颈。针对这个问题,在不减少预测模式和不增加系统资源的前提下,提出了一种新的结构,它通过利用原始像素进行模式判决和利用重构像素进行帧内预测的方法,可以使帧内预测与重构循环完全流水线实现,基本上达到了100%的硬件利用率,而且没有明显的PSNR损失。所提出的硬件结构可在215个时钟周期内完成一个宏块的帧内4×4预测。用SMIC 0.13μm工艺库综合,结果显示该结构最高可运行在250 MHz,面积约为116千门,可支持4 096×2 160@30 f/s(帧/秒)视频序列的实时编码。     

AVS解码器帧内预测并行自适应硬件实现

分析了AVS标准帧内预测的各种模式,在对各模式计算公式相似性进行分析的基础上,针除平面模式之外的其他5种预测模式提出了一种自适应的并行处理模块,可高速计算预测像素值,在各种模式下处理完整的8×8块最少一个需时钟周期,最多6个时钟周期,缩减了电路面积,简化了控制逻辑.处理能力达到AVS标准1920×1080,30 f/s(帧,秒)的高清视频要求.     

H.264/AVC帧内4×4块预测模式判别的改进算法

H.264提供了4×4的亮度块帧内预测,其共有9种预测模式.在判断其预测模式中要求4×4块的每种预测模式都要判断,因此计算复杂度很高.有效减少4×4块预测模式的判断次数,在实时视频编码过程中很有价值.基于此,提出了一种帧内4×4块预测模式判断提前退出的优化算法,并对其进行了试验,得到了很好的效果.     

H.264帧内模式快速判决

针对在降低H.264视频编码复杂度方面提出的一种有效的4×4帧内预测模式判决方法。研究发现,在基于变换域的帧内预测模式下,当一个块的局部边缘方向一致时,可以得到一种很好的预测,由此可以滤除大部分帧内模式。通过滤除大部分帧内模式,只需考虑剩余具有较高概率的4×4帧内预测模式,对于这些模式需要进行率失真优化处理。仿真结果表明,本判决方法在保证图像质量和压缩比不变的情况下,能够使计算量大大降低。     

一种H.264/AVC帧内4x4预测算法的高效流水线结构

H.264编码器中的帧内4x4预测部分具有严重的数据依赖性,它的硬件化设计很难采用流水线实现,从而导致关键路径很长,硬件利用率很低,成为H.264编码器设计中的一个瓶颈。针对这个问题, 在不减少预测模式和不增加系统资源的的前提下,本文提出了一种新的结构,它通过利用原始像素进行模式判决和利用重构像素进行帧内预测的方法,可以使帧内预测与重构循环完全流水线实现,基本上达到了100%的硬件利用率,而且没有明显的PSNR的损失。本文所提出的硬件结构可在215个时钟周期内完成一个宏块的帧内4x4预测。用SMIC 0.13um工艺库综合,结果显示该结构最高可运行在250M,面积约为116K门,可支持4096x2160@30fps视频序列的实时编码。     

H.264解码器帧内预测模块的优化

提出一种H.264帧内预测的优化实现结构.该结构对帧内预测模块做了两方面的优化:一是结合环路滤波,去除了目前帧内预测模块中片上空间(SRAM)的冗余存储;二是针对4×4亮度块的预测模式获取过程相对复杂的特点,采取了预先判断并存储相邻块预测模式的措施.提出的帧内预测结构在减少片上存储空间需求的同时,减少了处理器和片外存储空间(SDRAM)的数据交互次数.由实验结果可知,相对于优化前,帧内预测模块的性能提高了10％以上.     

一种高并行度的H.264帧内预测器的VLSI设计

分析了帧内预测的17种模式,对于每个4×4大小块的16个像素点的不同模式的预测公式之间的相同运算,采用数字强度缩减的方法去除计算的冗余,提出了一种高并行度的帧内预测器,可以每个时钟周期处理16个像素点的预测值。基于SMIC0.18μm工艺,用verilog对该设计进行了VLSI实现,综合后的电路的关键路径最大时延为10ns,电路规模不超过1.4万门,数据吞吐率可以达到1600Msamples/s。从实现结果来看,与采用可重构方法的设计相比,该设计在相同的并行度下减小了电路面积,简化了控制逻辑。     

一种基于预测频度的AVS／H．264快速4×4帧内预测模式选择算法

提出了一种新颖的4×4快速帧内预测模式选择算法。该算法挖掘了帧内预测算法本身的部分性质，即不同像素在不同预测方向中的频度权重不同这个特点，同时利用了子块的平滑性与相关性，设计了3个能快速命中预测模式的自适应门限。实验表明本算法能在几乎不改变PSNR的情况下大幅度降低4×4帧内预测复杂度。     

一种基于预测频度的AVS/H.264快速4×4帧内预测模式选择算法

提出了一种新颖的4×4快速帧内预测模式选择算法。该算法挖掘了帧内预测算法本身的部分性质,即不同像素在不同预测方向中的频度权重不同这个特点,同时利用了子块的平滑性与相关性,设计了3个能快速命中预测模式的自适应门限。实验表明本算法能在几乎不改变PSNR的情况下大幅度降低4×4帧内预测复杂度。     

Improved lossless intra coding for H.264/MPEG-4 AVC.

A new lossless intra coding method based on sample-by-sample differential pulse code modulation (DPCM) is presented as an enhancement of the H.264/MPEG-4 AVC standard. The H.264/AVC design includes a multidirectional spatial prediction method to reduce spatial redundancy by using neighboring samples as a prediction for the samples in a block of data to be encoded. In the new lossless intra coding method, the spatial prediction is performed based on samplewise DPCM instead of in the block-based manner used in the current H.264/AVC standard, while the block structure is retained for the residual difference entropy coding process. We show that the new method, based on samplewise DPCM, does not have a major complexity penalty, despite its apparent pipeline dependencies. Experiments show that the new lossless intra coding method reduces the bit rate by approximately 12% in comparison with the lossless intra coding method previously included in the H.264/AVC standard. As a result, the new method is currently being adopted into the H.264/AVC standard in a new enhancement project.     

A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding

Prediction, including intra prediction and inter prediction, is the most critical issue in H.264/AVC decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and account for up to 80% of the total decoding cycles. In this paper, we present the design and VLSI implementation of a novel power-efficient and highly self-adaptive prediction engine that utilizes a 4 times 4 block level pipeline. Based on the different prediction requirements, the prediction pipeline stages, as well as the correlated memory accesses and datapaths, are fully adjustable, which helps to reduce unnecessary decoding operations and energy dissipation while retaining the fixed real-time throughput. Compared with conventional designs, this paper has the advantage of higher efficiency and lower power consumption due to the elimination of all redundant operations and the wide employment of the pipeline and parallel processing. Under different prediction modes, our design is able to decode each macroblock within 500 cycles. A prototype H.264/AVC baseline decoder chip that utilizes the proposed prediction engine is fabricated with UMC 0.18-mu CMOS 1P6 M technology. The prediction engine contains 79 K gates and 2.8 kb single-port on-chip SRAM, and occupies half of the whole chip area. When running at 1.5 MHz for QCIF 30 f/s real-time decoding, the prediction engine dissipates 268 muW at a 1.8-V power supply.     

Error Concealment Using Intra‐Mode Information Included in H.264/AVC‐Coded Bitstream

The H.264/AVC standard has adopted new coding tools such as intra‐prediction, variable block size, motion estimation with quarter‐pixel‐accuracy, loop filter, and so on. The adoption of these tools enables an H.264/AVC‐coded bitstream to have more information than was possible with previous standards. In this paper, we propose an effective spatial error concealment method with low complexity in H.264/AVC intra‐frame. From information included in an H.264/AVC‐coded bitstream, we use prediction modes of intra‐blocks to recover a damaged block. This is because the prediction direction in each prediction mode is highly correlated to the edge direction. We first estimate the edge direction of a damaged block using the prediction modes of the intra‐blocks adjacent to a damaged block and classify the area inside the damaged block into edge and flat areas. Our method then recovers pixel values in the edge area using edge‐directed interpolation, and recovers pixel values in the flat area using weighted interpolation. Simulation results show that the proposed method yields better video quality than conventional approaches.     

Algorithm analysis and architecture design for rate distortion optimized mode decision in high definition AVS video encoder

There are abundant intra and inter prediction modes in the AVS video coding standard. Rate distortion optimized mode decision can fully utilize this flexibility to improve the spatio-temporal prediction efficiency and maximize the coding efficiency. However, the implementation complexity is dramatically high due to huge throughput burden. Hardware oriented mode decision algorithm is tailored for VLSI implementation in this work for high definition video coding. Mode preselection is employed to alleviate the dramatic throughout burden. Also, intelligent pipeline scheduling mechanism is proposed to break the intrinsic data dependency in intra prediction, which is directly related with mode decision. The proposed simplified algorithm is well-suited for hardware implementation with small performance penalty. Finally, the VLSI architecture is proposed with good trade off between circuit consumption and rate distortion performance.     

Novel intra prediction via position-dependent filtering

This paper presents a novel intra prediction algorithm, named position-dependent filtering (PDF), to improve the intra prediction accuracy. Different from the existing schemes where the samples along one prediction direction are predicted with the same set of filtering coefficients, in the proposed PDF, position-dependent filtering coefficients are employed, i.e., different sets of filtering coefficients are pre-defined for samples with different coordinates in one coding block. For each intra prediction mode, the set of linear filtering coefficients for each position within one block is obtained from off-line training using the least square method. Moreover, to further reduce the algorithm complexity, a simplified PDF (sPDF) is proposed. In sPDF, only a subset of reference samples are used for prediction and the others are discarded because of the minor contribution to intra prediction. The proposed algorithm has been implemented in the latest ITU-T VCEG KTA software. Experimental results demonstrate that, compared with the original KTA with new intra coding tool enabled, up to 0.53 dB of average coding gain is achieved by the proposed method, while applicable computational complexity is retained for practical video codecs.     

基于块参考像素特征的快速帧内预测模式选择新算法

帧内预测是H.264采用的一种编码新技术。与以前的编码标准相比,H.264编码性能有了很大的提高,但同时编码复杂度和计算量也明显增加。该文研究了提高H.264编码速度的途径,着重分析了帧内预测模式快速选择的问题。经过分析发现,4×4亮度块的参考像素亮度值通常具有相似性,对应地,4×4亮度块的9种预测模式所得的预测结果也是相近的。根据4×4亮度块参考像素的这一特征,该文提出了一种基于4×4亮度块参考像素特征的快速帧内预测模式选择算法。实验结果说明了该文算法的有效性,与H.264编码器JM92相比,该算法的计算量减少了46%,而编码质量、PSNR和输出码率保持基本不变。     

AVS编码器中帧内预测模块的硬件设计

根据AVS标准中帧内预测算法的特点,提出了一种应用于AVS高清实时编码器的帧内预测硬件设计方案.该设计中将亮度和色度预测共用一个预测单元,采用6路数据并行流水处理的结构,提高了处理速度.同时在分析AVS帧内预测各模式算法的基础上,结合移位寄存器操作实现各模式运算单元的进一步资源共享,简化了参考数据选择机制,减少资源消耗.实验结果表明,该设计完全能够满足高清视频图像(1 920×1 080,30 f/s(帧/秒))实时编码要求.     

Enhanced pipelined architecture of H.264/AVC intra prediction

This paper presents a high-performance encoder for H.264/AVC intra prediction. Due to long data dependency loop of intra 4×4 prediction and complex algorithms, improving encoding speed turns into a stumbling block we have to face. To solve this problem, we first propose a pipelined method in and between macro blocks with new block processing order to accelerate the encoding speed. Benefiting from the pipelined method, reconstructed pixels of up-right blocks are available for two blocks in a macro block which could not take advantage of reconstructed pixels of up-right blocks in JM. So diagonal down left mode and vertical left mode are effective for these two blocks, which ultimately achieves a better bit-rate. Secondly, all 4×4 mode formula sharing method is proposed to reduce the redundancy of predicting formulas. Thirdly, streamlined reconstruction method is applied to improve the performance of reconstruction. CAVLC encoder with three parallel units is proposed to improve entropy coding speed significantly. As a result, it takes 268 cycles to encode a macro block. The experimental results indicate that synthesized into a 0.18 µm CMOS cell library, the new architecture only requires about 238K gates and it is able to encode 1080pHD video sequences at 30 frames per second (fps), at the operating frequency of 56 MHz.     

基于帧内预测模式的H.264/AVC视频信息嵌入算法

提出了一种基于帧内预测模式的H.264/AVC视频信息嵌入算法.在秘密信息进行嵌入时,根据人类视觉特性的掩蔽效应,筛选出I帧中纹理密集区域的4×4亮度块,确定为嵌入块.通过秘密信息调制4×4亮度块的预测模式最低有效位,完成秘密信息的嵌入.通过对算法进行仿真实验,证明本算法计算量小,能够实时处理.对视频载体影响小,有一定的嵌入容量,能够保证秘密信息的有效传输.