Complete high-performance cache system for the 80386

The 80386 is a high-performance third-generation microprocessor that is now standard in most top-of-the-range PCs. Like all similar processors operating at clock rates above 30 MHz, the 80386 must use cache memory if it is to operate efficiently. Without cache memory, the user must either pay a very high price for very fast RAM or employ slower memory by introducing wait states. This application note describes the 80386 bus interface and demonstrates how it can be interfaced to IDT cache tag RAMs to create a cache system. Although the report describes a relatively basic cache system, it covers all design considerations ranging from system timing to the programming of the PALs needed to implement the interface. A.C.     

Multichannel software event counter for the MC6809

Software can provide a cheap means of counting low-frequency events such as egg laying. A counting technique and driver program for this example are described.     

Enhancing MC68030 performance using the SN74ACT2155 cache

Texas Instruments highlights the important questions facing the system designer who needs to interface a cache to a fast microprocessor, giving an example solution using its cache chip     

Microprogrammable peripheral controller

One of the most talked about microprocessor applications in the computer peripheral industry is device control. This paper presents a microsequencer-based general-purpose microprogrammable peripheral controller. This controller enables efficient and easy coupling between a wide range of I/O buses and peripherals. As an example, design details are given for interfacing a card reader onto an IBM standard I/O bus.     

Switched memory for multiprocessor MC6809E systems

An increasing interest is being shown in the use of multimicroprocessor systems in a variety of applications. It is often desirable that the constituent processors have a fast communications link for the sharing of data and/or results. Both of these aims can be achieved by the sharing of blocks of memory between the two or more processors; this method has the added advantage of little, or in some cases no, software overhead. The design of a shared memory system for Motorola MC6809E microprocessors is presented.     

The MC68020, a true 32-bit microprocessor

The Motorola MC68020 is one of the first 32-bit microprocessors. The 68020 is part of the 68000 family, which has a register-based architecture. In the 68020 a number of instructions and addressing modes, and some data types, have been implemented, to increase input and to help in the implementation of modular high-level languages and their associated constructs and data structures. The 68020 is made with the HCMOS process.     

Using a microprocessor in high performance liquid chromatography

The background and use of a microprocessor-controlled liquid chromatograph to carry out the automatic optimization of high performance liquid chromatography (HPLC) separations is discussed. The procedure is based upon the use of the modified sequential simplex algorithm to select the optimum composition of a three component mobile phase. The way in which the simplex algorithm is incorporated into a program and the hardware used is described. The use of this approach provides the chromatographer with the ability to optimize HPLC separations without requiring either extensive theoretical knowledge or a great expenditure of time and effort.     

Interactive component extraction from fEEG, fNIRS and peripheral biosignals for affective brain-machine interfacing paradigms

This paper investigates whether some well understood principles of human behavioral analysis can be used to design novel paradigms for affective brain-computer/machine interfaces. This is achieved by using the visual, audio, and audiovisual stimuli representing human emotions. The analysis of brain responses to such stimuli involves several challenges related to the conditioning of brain electrical responses, extraction of the responses to stimuli and mutual information between the several physiological recording modalities used. This is achieved in the time-frequency domain, using multichannel empirical mode decomposition (EMD), which proves very accurate in the joint analysis of neurophysiological and peripheral body signals. Our results indicate the usefulness of such an approach and confirm the possibility of using affective brain-computer/machine interfaces.     

80C196MC/MD单片机多个中断程序的同步问题

高性能１６位单片机８ＸＣ１９６ＭＣ／ＭＤ具有指令丰富、外设完善、功能强大等特点。其外设间的协同工作，在测控领域应用中是十分必要的。本文介绍了其外设中断服务程序间的同步控制概念和程序设计应注意的问题。     

68000 and the Pick operating system

The Pick operating system was developed 20 years ago and has always been thought of as a ‘dark secret’. However, it has been ported onto the 68000 chip, and is proving successful on micros. It is based on a database design, and features variable length fields and the ability to have multivalues. Programming can be carried out in Data BASIC.     

FORTH and microprocessor applications at the Royal Greenwich Observatory

In common with other activities that make extensive use of electronics and computing, astronomy has been profoundly affected by the availability of minicomputers and microprocessors. These devices have brought with them a revolution both in the quality of astronomical data and in the ease with which that data may be obtained; many exciting astronomical research results have been obtained as a direct consequence. This paper describes the microprocessor program at RGO, including the hardware, why it was chosen and how it is possible to cope with rapid technological changes, and the software which unifies the different processors. It describes highlights of the projects for which microprocessors have been used so far, and discusses some likely future developments in astronomical applications.     

Standalone low-cost interface,controller and emulator for the apple II

An I/O Interface card for the Apple II microcomputer is described. The card provides a 6522 versatile interface adaptor and a 2716 EPROM. An onboard 6502 microprocessor and 1 k RAM enable the interface card to be used independently of the Apple II as a standalone microcomputer controller. The card thus serves as a simple incircuit emulator for itself when it is in the Apple II.     

Programming the 68000 in high-level language for VME

Many choices of VME hardware module now exist but software still continues to be the major cost in systems development. As development teams face more complex projects, productivity can be improved by four approaches: the use of standard system architecture, the use of software building blocks, the use of better tools and an increase in the level of software engineering management. Some characteristics of realtime systems programming are presented. Next an overview of the VMEbus is given. Then a target operating environment for 68000-based applications in PASCAL is described. The software components are called pSOS, pHILE and pROP. These provide the realtime executive or kernel, file management system and runtime support for PASCAL respectively. Languages other than PASCAL can be used with pSOS and pHILE, but a preference is expressed for PASCAL over the language C.     

On the design of on-chip instruction caches

Cache memories reduce memory latency and traffic in computing systems. Most existing caches are implemented as board-based systems. Advancing VLSI technology will soon permit significant caches to be integrated on chip with the processors they support. In designing on-chip caches, the constraints of VLSI become significant. The primary constraints are economic limitations on circuit area and off-chip communications. The paper explores the design of on-chip instruction-only caches in terms of these constraints. The primary contribution of this work is the development of a unified economic model of on-chip instruction-only cache design which integrates the points of view of the cache designer and of the floorplan architect. With suitable data, this model permits the rational allocation of constrained resources to the achievement of a desired cache performance. Specific conclusions are that random line replacement is superior to LRU replacement, due to an increased flexibility in VLSI floorplan design; that variable set associativity can be an effective tool in regulating a chip's floorplan; and that sectoring permits area efficient caches while avoiding high transfer widths. Results are reported on economic functionality, from chip area and transfer width to miss ratio. These results, or the underlying analysis, can be used by microprocessor architects to make intelligent decisions regarding appropriate cache organizations and resource allocations.     

Reliable microprocessor control for drive-by-wire car steering for the disabled

In a drive-by-wire steering system for the disabled driver, the safety of the system depends on the reliability of the electronic components. There is however another constraint, that of cost. A microprocessor-based system appears to be the most appropriate type. It was found however that three independent channels were needed to get the required level of reliability. The prototype system described here illustrates some of the problems and some of the potential solutions. Important among these is the balancing of the computations between the parallel channels.     

Undocumented features of the X5 flag belt in the 8085 microprocessor: Many 8085 users have found problems in comparing signed operands using conventional methods.

In comparing two signed operands, it may be shown theoretically that, if operand 1 is greater than operand 2, then flag bit X5 is reset; otherwise X5 is set. In this paper, JX5 and JNX5 instructions are used for checking the set and reset conditions, respectively, of X5 in proper branching within a program. The above criteria are verified experimentally using the SDK-85 design kit.     

Performance monitoring of the EC - 1030 system by a microprocessor - based monitor

This paper presents a M6800 microprocessor based hardware monitor for measuring certain selected parameters of the EC-1030 computer system. The motivation for this work was to get an insight into the operation of the system under the present work load and use these results towards improvement and design studies. The three main classes of quantitative indices of computer system performance/productivity, responsiveness and use have been measured using hardware and software tools. This paper describes the hardware monitor design and discusses the measurements made.     

使用电场传感器MC33794的模拟游戏控制器

本文通过使用Freescale公司的电场传感器MC33794设计并实现了一种新型的模拟游戏控制器。该游戏控制器使用C8051F310作为主控芯片,通过非接触方式感知手掌的姿态,转换为模拟量控制信息,起到能够在游戏的各个方向上控制力度的作用。