具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.     

A Low-Dropout Regulator for SoC With Q-Reduction

A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (V_THN ap 0.55 V and |V_THP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current     

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm². The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV V_DO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.     

一种新颖的LDO线性稳压器

设计了一种新颖的LDO线性稳压器.该LDO工作于负电源,具有微功耗、自身固定-5 V输出、外接反馈电阻可实现可调输出等特点.基于0.6 μm SOI CMOS工艺进行流片.测试结果表明,该电路输入电源电压VIN为-2～-18 V,可调输出电压为-1.3 V～VIN+0.5 V@Iour=15mA.该LDO功耗低,室温下空载静态电流约4.8μA,并且几乎不随VIN变化.内部带隙电压基准采用β二阶补偿,结构简单,温度系数为1.28×10-5/℃.线性调整率为0.015％,负载调整率为0.85 Ω.     

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor.      

一种双路输出低压差电源的研制

文章介绍了一种CMOS双路输出低压差电源。电路设计中，采用E／DNMOS基准，用PMOS管作调整管；电路实现采用1．5μm硅栅自对准E／DCMOS工艺。该低压差电源可提供输出电流为1A的3．3V固定输出(压差为0．6V)和1A可调输出，并具有短路保护和过压保护等功能。     

一种低压差+5 V三端电源的研制

介绍了一种CMOS低压差 5 V三端稳压源.在电路设计上,将PMOS管作为调整管,采用带隙基准和NMOS基准两种结构,重点讨论了影响低压差电源的几个因素;在工艺上,采用硅栅自对准CMOS工艺,做出了100 mA时压差为0.3 V的 5 V三端电源.采用NMOS基准的三端稳压源,其静态电流和电源抑制比等参数优于采用带隙基准的三端稳压源.     

低静态电流低压降CMOS线性稳压器

设计了一种100 mA低静态电流、低压降CMOS线性稳压器.通过使用与一般线性稳压器相类似的频率补偿方法,这种低压差线性稳压器获得了低静态电流,很好的电源调整率和负载调整率,以及很高的PSRR值.在0.5 μm工艺下的仿真结果表明,其消耗的静态电流只有5 μA,电源调整率和负载调整率分别为0.02 mV/V和0.002 mV/mA;在100 Hz时,其PSRR值为-90 dB,负载电容只有100 pF,可以很容易地集成到电路中.     

A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier

Low $1/f$ noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and $1/f$ noise accumulation at the chopping frequency, a first-order digital ${Sigma}{Delta}$ noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 ${hbox{nV}}/{surd}{hbox{Hz}}$ and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced $1/f$ noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 $mu{hbox{s}}$ settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 $mu{hbox{m}}$ CMOS process with five layers of metal, occupying 0.88 ${hbox{mm}}^{2}$.      

Full On-Chip CMOS Low-Dropout Voltage Regulator

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.     

一种高PSR低静态电流LDO设计

设计了一种基于0.18 μm BCD工艺的高电源抑制(PSR)低静态电流低压差线性稳压器(LDO)。详细分析了多条电源噪声传递路径对系统PSR的影响。为优化系统中低频段PSR,设计了一种双轨供电的三级误差放大器。此外还引入了预稳压单元,降低了电压基准模块对系统低频段PSR的影响。为降低系统的静态电流,设计了一种基于耗尽管的超低静态电流电压基准。仿真结果表明,该LDO在不同输出电压下静态电流仅5 μA,并且在250 mA负载电流内PSR<-110 dB @1 kHz,PSR<-55 dB @1 MHz。     

一种适用于LDO的新型斜坡软启动电路

提出了一种新型的应用于低压差线性稳压器(LDO)的斜坡软启动电路,其采用两路斜坡使能信号以及一路斜坡基准信号,消除了电源上电时产生的浪涌电流。该斜坡软启动电路已应用于一款LDO中,并采用0.35 μm CMOS 工艺实现流片,其仅占LDO有效面积的8.3%,消耗电流仅600 nA。仿真以及测试结果显示,采用该软启动电路之后,LDO的上电浪涌电流得到有效抑制。LDO在最差情况下的线性调整率为2.7 mV/V,负载调整率为0.064 mV/mA。     

面向片上系统的无片外电容CMOS低压差稳压器

提出了一种面向片上系统、不依赖片外电容的CMOS低压差稳压器.通过采用片上极点分离技术和片上零极点抵消技术,保证了没有片外电容情况下低压差稳压器的稳定性.芯片通过华润上华0.5/μm CMOS工艺进行了流片.芯片核心区域(不包括焊盘)尺寸为600μm×480μm.输入电压变化造成的输出电压变化偏差在±0.21%以内.静态电流为39.8μA.10kHz处的电源抑制比为-34dB.100Hz和100kHz处的输出噪声电流谱密度分别为1.65和0.89μV/√Hz.     

面向片上系统的无片外电容CMOS低压差稳压器

提出了一种面向片上系统、不依赖片外电容的CMOS低压差稳压器.通过采用片上极点分离技术和片上零极点抵消技术,保证了没有片外电容情况下低压差稳压器的稳定性.芯片通过华润上华0.5/μm CMOS工艺进行了流片.芯片核心区域(不包括焊盘)尺寸为600μm×480μm.输入电压变化造成的输出电压变化偏差在±0.21%以内.静态电流为39.8μA.10kHz处的电源抑制比为-34dB.100Hz和100kHz处的输出噪声电流谱密度分别为1.65和0.89μV/√Hz.     

一种新颖的BiCMOS高精度LDO线性稳压电路

设计了一种改进结构的用于锂离子和锂聚合物电池充电管理芯片的高精度、宽电源电压范围LDO线性稳压电路,电路采用0.8μm N阱BiCMOS高压工艺制作。Hspice仿真结果表明,在温度从-20℃到100℃变化时,其温度系数约为±28 ppm/℃;电源电压从4.5 V到25 V变化时,最坏情况下其线性调整率为0.038 mV/V;负载电流从0到满载2 mA变化时,其负载调整率仅为1.28 mV/mA。     

一种采用新颖的双重自适应补偿的低静态电流LDO稳压器的设计

设计了一种采用双重自适应补偿的两级结构LDO线性稳压器,该补偿技术能够产生两个随负载变化的零点以抵消不同负载条件下的极点变化带来的影响,从而保证系统的稳定性.与传统的设计方法相比,该补偿方法几乎不消耗电流,文中设计的LDO静态电流小于1μA,并且采用折返式电流限制,减小了芯片的功耗.采用该双重自适应补偿的LDO已在Hynix O.5μm CMOS工艺线投片,当负载电流为300mA时,漏失电压为150mV,线性调整率为2mV/V,负载调整率为0.75%.测试结果表明,采用该双重自适应补偿结构的LDO工作良好.     

一种采用新颖的双重自适应补偿的低静态电流LDO稳压器的设计

设计了一种采用双重自适应补偿的两级结构LDO线性稳压器,该补偿技术能够产生两个随负载变化的零点以抵消不同负载条件下的极点变化带来的影响,从而保证系统的稳定性. 与传统的设计方法相比,该补偿方法几乎不消耗电流,文中设计的LDO静态电流小于1μA,并且采用折返式电流限制,减小了芯片的功耗. 采用该双重自适应补偿的LDO已在Hynix 0.5μm CMOS工艺线投片,当负载电流为300mA时,漏失电压为150mV,线性调整率为2mV/V,负载调整率为0.75%.测试结果表明,采用该双重自适应补偿结构的LDO工作良好.     

超低压差CMOS线性稳压器的设计

设计出一种输出电流为300mA且具有微功耗超低压差低噪声性能的单片CMOS线性稳压器,对其电路结构及工作原理进行了分析并给出各子电路模块的设计。该稳压器具有过流过热保护,工作电压范围为2．5V～6V。基于现代公司的0．6μm CMOS工艺模型,Hspice模拟结果表明其输入输出压差的典型值分别为0．4mV@1mA和120mV@300mA,静态电流的典型值为90μA。     

一种新型的全片内低噪声CMOS低压差线性稳压器

提出了一种全片内集成的低噪声CMOS低压差线性稳压器(LDO).首先建立传统LDO的噪声模型,分析了关键噪声来源并提出采用低噪声参考电压源来降低LDO输出噪声的方法.其次,提出一种带数字校正的基于阈值电压的低噪声参考电压源,用TSMC 0.18μm RF CMOS工艺设计并完成了为低相位噪声锁相环(PLL)电路供电的全片内集成低噪声LDO的流片和测试.该LDO被集成于高性能射频接收器芯片中.仿真结果表明,LDO的输出噪声低于26nV/√Hz@100kHz,14nV/√Hz@1MHz,电源抑制比达到-40dB@1MHz,全频率范围内低于-34dB.测试结果表明采用该低噪声LDO的PLL电路与采用传统LDO的PLL电路相比,其相位噪声降低6dBc@lkHz,低2dBc@200kHz.