Analog circuits for modeling biological neural networks: design andapplications

Computational neuroscience is emerging as a new approach in biological neural networks studies. In an attempt to contribute to this field, we present here a modeling work based on the implementation of biological neurons using specific analog integrated circuits. We first describe the mathematical basis of such models, then present analog emulations of different neurons. Each model is compared to its biological real counterpart as well as its numerical computation. Finally, we demonstrate the possible use of these analog models to interact dynamically with real cells through artificial synapses within hybrid networks. This method is currently used to explore neural networks dynamics.     

Analog circuits in ultra-deep-submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.     

Analog CMOS deterministic Boltzmann circuits

CMOS circuits implementing an analog neural network (ANN) with on-chip deterministic Boltzmann learning (DBL) and capacitive synaptic weight storage have been designed, fabricated, and tested. Weights are refreshed by periodic repetition of the training data. The circuits were used to build a 12-neuron, 132-synapse ANN that performed well in a variety of learning experiments, including a 36-input to 4-output mapping problem. Adaptive systems such as those described here can compensate for imperfections in the components from which they are constructed and therefore can be built using simple silicon area-efficient analog circuits. The test results indicate that deterministic Boltzmann ANNs can be implemented efficiently using analog CMOS circuitry     

ANALOG CIRCUIT IMPLEMENTATION OF NEURAL NETWORK WITH HIGH PRECISION WEIGHTS

A current-mode MOS neuron circuit with 4-bit programmable weights is presented by using CMOS technology. The weights of the neurcn have high resolution and also can easily be digitally stored. The resolution can be extended into high levels such as 8-bit, etc. by the design methodology presented in this paper. The operational principle of the neuron is discussed. Circuit simulation has been made by use of SPICE II. The results give a good agreement for the design requirements.     

DECISION OF OPTIMAL HOPFIELD NEURAL NETWORK MODEL OF COMBINATIONAL CIRCUITS

By use of Hopfield model and basis solution of homogeneous linear equations which are established in accordance with consistent state, a practical decision method for the existence of optimal Hopfield model of combinational circuits is provided. Finally, an example is given.     

基于小波神经网络的模拟电路故障诊断方法研究

小波变换是一种时频分析方法,具有多分辨率特性,被誉为数学显微镜,而BP神经网络具有较好的泛化能力,很适合于判断电路状态属于哪种故障类型的分类问题。本文将二者结合起来,采用基于小波神经网络的模拟电路故障诊断方法。应用小波变换对模拟电路幅频响应的采样信号进行故障特征提取,然后利用BP神经网络对各种状态下的特征向量进行分类决策,实现模拟电路的故障诊断。通过对电路进行仿真,证明该方法能够实现故障检测及定位,具有准确率高的特点。     

Chaos in electronic circuits

This paper describes three extremely simple electronic circuits in which chaotic phenomena have been observed. The simplicity of the circuits allows one to i) build them easily, ii) confirm the observed phenomena by digital computer simulation, and in some cases iii) rigorously prove the circuit is indeed chaotic. A consequence of i) is that the interested reader can build, and then see and even listen to chaos. It is to be emphasized that these circuits are not analog computers. They are real physical systems.     

Analog statistical simulation for bipolar integrated circuits

Analog circuit design automation continues to gain attention in methods to improve, automate, and reduce design cycle time. These techniques address the needs of improving design for functionality, however the importance of design for manufacturability continues to be neglected. The emphasis of design for manufacturability is shown when the quality of a part is measured. Parts designed with no consideration for process/design variations result in poor yield. To address the need in analog design for manufacturability, new techniques that involve the areas of physical process, geometric modeling of electrical parameters, and statistical simulation techniques using independent process parameters, yield and Cpk analysis are defined and implemented. Results from these techniques provide the analog designer with the ability to simulate and predict circuit quality with process and design variations. To support the defined techniques, a design tool called MSTAT (Motorola Statistical Analysis Tool) is developed. Results of these techniques accompanied with MSTAT output is presented.     

Fault detection in analogue circuits using hybrid evolutionary algorithm and neural network

With the development of analog integrated circuits technology and due to the complexity, and various types of faults that occur in analog integrated circuits, fault detection is a new idea, has been studied in recent decades. In this paper a three amplifier state variable filter is used as circuit under test (CUT) and, a hybrid neural network is proposed for soft fault diagnosis of the CUT. Genetic algorithm (GA) has the powerful ability of searching the global optimal solution, and back propagation (BP) algorithm has the feature of rapid convergence on the local optima. The hybrid of two algorithm will improve the evolving speed of neural network. GA-BP scheme adopts GA to search the optimal combination of weights in the solution space, and then uses BP algorithm to obtain the accurate optimal solution quickly. Experiment results show that the proposed GA-BP scheme is more efficient and effective than BP algorithm.     

基于神经网络信息融合技术的模拟电路故障诊断

研究了神经网络信息融合技术在模拟电路故障诊断中的应用。利用BP神经网络建立信息融合中心,对多传感器数据进行融合处理,减少模拟电路故障诊断的不确定性。对标准电路的输出电压与电源电流特征信息,及两者融合信息的故障诊断性能比较,表明神经网络信息融合方法用于模拟电路故障诊断是有效和可行的。     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

An associative memory based on an electronic neural network architecture

A high-density matrix of α-Si resistors was made to demonstrate a new type of parallel-processing associative memory consisting of an interconnected array of analog amplifiers. The 22 × 22 resistor matrix was made using a technology compatible with conventional VLSI processing. This demonstration circuit can recall up to four 22- bit memories in 1 to 10 µs while correcting errors in the input word of at least 5 bits. This function is difficult to perform efficiently in conventional digital hardware and is the basis for solving a variety of pattern-recognition problems including vision and speech.     

粒子群算法优化特征和神经网络的模拟电路故障诊断

模拟电路受到自身特性和外界环境的影响,故障变化具有非线性、时变性,针对当前模拟电路故障诊断模型的特征和分类器参数不匹配的难题,提出一种粒子群算法选择特征和神经网络的模拟电路故障诊断模型。首先对当前模拟电路故障诊断现状进行分析,指出它们存在的缺陷;然后提取模拟电路故障诊断特征,利用神经网络作为模拟电路故障诊断分类器;最后采用粒子群算法对模拟电路故障特征与神经网络参数进行优化,在Matlab 2012平台进行了仿真实验。结果表明,该模型的模拟电路故障诊断性能要远远优于其他参比模型,具有广泛的应用前景。     

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.