基于TDR技术的HDMI高速差分总线特性阻抗的测量

高清多媒体接口(HDMI)技术正在迅猛的增长,传输速率也越来越快,遇到的高速连接的挑战也越来越大。通过时域反射(TDR)技术对HDMI的高速差分总线进行特性阻抗测量,可以直接的测量和显示印刷电路板(PCB)走线以及连接器和线缆的阻抗连续性能,对于诊断和分析HDMI系统高速连接的可靠性和稳定性起到非常重要的作用。     

一种基于TDR测量的高速连接器的MMTL模型

该文提出了一种全新的高速连接器时域模型MMTL(Multi-segment Multiple Transmission Line model)。该模型克服了MLC模型不稳定和仿真效率低的缺点,具有直观、精度可控、便于优化等优点。实验结果表明,该文所建模型精度高,与实际测量的最大误差小。     

J-substitution algorithm in magnetic resonance electrical impedance tomography (MREIT): phantom experiments for static resistivity images

Recently, a new static resistivity image reconstruction algorithm is proposed utilizing internal current density data obtained by magnetic resonance current density imaging technique. This new imaging method is called magnetic resonance electrical impedance tomography (MREIT). The derivation and performance of J-substitution algorithm in MREIT have been reported as a new accurate and high-resolution static impedance imaging technique via computer simulation methods. In this paper, we present experimental procedures, denoising techniques, and image reconstructions using a 0.3-tesla (T) experimental MREIT system and saline phantoms. MREIT using J-substitution algorithm effectively utilizes the internal current density information resolving the problem inherent in a conventional EIT, that is, the low sensitivity of boundary measurements to any changes of internal tissue resistivity values. Resistivity images of saline phantoms show an accuracy of 6.8%-47.2% and spatial resolution of 64 x 64. Both of them can be significantly improved by using an MRI system with a better signal-to-noise ratio.     

埋入堆叠芯片封装结构的电学仿真和优化

埋入堆叠芯片技术在实现封装小型化的同时,增加了封装电学设计的复杂性。以一个数字系统为例,详细阐述了埋入堆叠芯片封装结构的电学设计过程。利用电磁仿真软件提取了该封装结构的寄生参数,并通过S参数、延时、反射分析,确定长绑定线为影响链路信号质量的关键因素,其影响直接限制了埋入堆叠芯片技术的应用范围。运用RLC传输线模型分析了长绑定线造成大的信号质量衰减的原因。最后,提出了一种大幅减短绑定线长度并提升链路电学性能的优化结构,拓展了此技术在高速领域的应用。眼图的对比结构表明,新结构能降低链路的阻抗失配,减小信号延时,并大大改善高速信号的质量。     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

射频连接器与微带线组件焊接过渡段阻抗补偿研究

射频连接器与微带线组件常用于通信系统电路中,而组件焊接过渡段的阻抗不连续会使电路中的信号损耗增大.针对该问题,本文对射频连接器与微带线组件焊接过渡段进行研究,基于传输线理论,建立焊接过渡段的等效电路模型.讨论了焊接过渡段特征阻抗不连续的原因,同时提出了补偿优化方案.此外,通过电磁场与电路的联合仿真,提取出补偿前后等效电路模型的电参数,从等效电路模型的角度分析了补偿方案对组件过渡段复杂电磁特性的影响.有限元仿真分析与实验测试结果显示,补偿后组件的性能显著提高,证明了补偿方案有效可行.     

一种宽频带二元微带天线阵的设计与制作

设计了一种连续旋转馈电方式下层叠结构的双单元圆极化微带天线阵。讨论了利用调谐支节优化层叠结构微带天线阻抗带宽的方法,并在此基础上引入连续旋转馈电方式组成了二元微带天线阵。制作并测试了相应的天线阵,结果表明:采用层叠结构可以有效扩展微带天线的阻抗带宽,同时提高了天线增益,连续旋转馈电技术则提高了天线阵的圆极化纯度,测试结果与仿真吻合较好。     

Analyze and Design High-Speed Power Delivery Networks Using New Multiinput Impedances in Printed Circuit Boards

In this paper, a new input impedance, the multiinput impedance, which includes all information of the full impedance matrix, is proposed to accurately analyze and design planar power delivery networks (PDNs) in high-speed printed circuit boards and packages. The multiinput impedance includes all of the potential impacts of the other operating active power ports in both low and high frequencies. A systematical power-delivery-network analysis and design method using the multiinput impedance is developed. The global and local characteristics of the decoupled PDN are well demonstrated by the multiinput impedance, which make the analysis and design of the modern decoupled PDNs more accurate and reliable. Numerical and measured results show that the proposed multiinput impedance can characterize both the global and local characteristics of the planar PDNs with high accuracy.      

Reduction of Transient Far-End Crosstalk Voltage and Jitter in DIMM Connectors for DRAM Interface

The transient far-end crosstalk voltage and the crosstalk-induced jitter of dual in-line memory module (DIMM) connectors are reduced by about 80% by increasing the mutual capacitance between DIMM connector pins with the additional interdigitated-comb-shaped metal-stub patterns on the motherboard. It was confirmed by the far-end crosstalk voltage waveform measurements using TDR and the eye diagram measurements at the data rates of 15 Mbps, 100 Mbps, and 3 Gbps. This reduction technique can be applied to the connectors where the inductive coupling ratio is larger than the capacitive coupling ratio.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Broadband Rational Macromodeling Based on the Adaptive Frequency Sampling Algorithm and the Partial Element Equivalent Circuit Method

The increasing operating frequencies in modern designs call for broadband macromodeling techniques. The problem of computing high-accuracy simulation models for high-speed interconnects is of great importance in the modeling arena. Nowadays, many full-wave numerical techniques are available that provide high accuracy, often at a significant cost in terms of memory storage and computing time. Furthermore, designers are usually only interested in a few electrical quantities such as port voltages and currents. So, model order reduction techniques are commonly used to achieve accurate results in a reasonable time. This paper presents a new technique, based on the partial element equivalent circuit method, which allows to generate reduced-order models by adaptively selecting the complexity (order) of the macromodel and suitable frequency samples. Thus, the proposed algorithm allows to limit the computing time while preserving the accuracy. Validation examples are given.     

Experimental and Analytical Studies of the Connector Insertion Phase

Studies of connectors for electric and electronic automotive systems have been and still are being pursued. The electrical connector reliability mainly depends on the connector insertion force. This force is related to the contact force which is imposed by the connector design. A nonintrusive technique for contact force determination by deflection measurement of the contact spring during insertion phase using a laser device has been developed. The following insertion parameters during the insertion stroke can be measured: contact deflection which yields the contact force, insertion force, and contact resistance. Regarding the results for real connectors, an experimental sample of a connector based on a cylindrical pin crossed with a cylindrical spring is proposed in this paper. With this simple setup, an mathematical model was developed and permits analysis of the influence of each parameter (width, spring radius, etc). Based on analysis of the influence of the spring width and of the gap, this study offers the possibility of optimizing the design of such connectors for use in the automotive industry.      

Harmonic decomposition in PDE-based denoising technique for magnetic resonance electrical impedance tomography

Recent progress in magnetic resonance electrical impedance tomography (MREIT) research via simulation and biological tissue phantom studies have shown that conductivity images with higher spatial resolution and accuracy are achievable. In order to apply MREIT to human subjects, one of the important remaining problems to be solved is to reduce the amount of the injection current such that it meets the electrical safety regulations. However, by limiting the amount of the injection current according to the safety regulations, the measured MR data such as the z-component of magnetic flux density Bz in MREIT tend to have low SNR and get usually degraded in their accuracy due to the nonideal data acquisition system of an MR scanner. Furthermore, numerical differentiations of the measured Bz required by the conductivity image reconstruction algorithms tend to further deteriorate the quality and accuracy of the reconstructed conductivity images. In this paper, we propose a denoising technique that incorporates a harmonic decomposition. The harmonic decomposition is especially suitable for MREIT due to the physical characteristics of Bz. It effectively removes systematic and random noises, while preserving important key features in the MR measurements, so that improved conductivity images can be obtained. The simulation and experimental results demonstrate that the proposed denoising technique is effective for MREIT, producing significantly improved quality of conductivity images. The denoising technique will be a valuable tool in MREIT to reduce the amount of the injection current when it is combined with an improved MREIT pulse sequence.     

Electromagnetic analysis of multiconductor losses and dispersion in high-speed interconnects

A self-consistent electromagnetic analysis of multiconductor transmission lines is presented for high-speed, high-density MMIC's and VLSI interconnects. In contrast to classical approach, this analysis handles the multiconductor as normal dielectric with high conductivity in electromagnetic simulation. Therefore, dispersion and loss effects can exactly be described in this model. Examples of interconnect circuits with up to four conductors are analyzed for dispersion and frequency-dependent losses. Propagation characteristics of multimode along symmetrical and asymmetrical multiconductor are obtained. Some inherent influences of losses on high-density interconnects and physical dependence of these effects are also discussed.     

Noninvasive imaging of bioimpedance distribution by means of current reconstruction magnetic resonance electrical impedance tomography

We have developed a novel magnetic resonance electrical impedance tomography (MREIT) algorithm-current reconstruction MREIT algorithm-for noninvasive imaging of electrical impedance distribution of a biological system using only one component of magnetic flux density. The newly proposed algorithm uses the inverse of Biot-Savart Law to reconstruct the current density distribution, and then, uses a modified J-substitution algorithm to reconstruct the conductivity image. A series of computer simulations has been conducted to evaluate the performance of the proposed current reconstruction MREIT algorithm with simulation settings for breast cancer imaging applications, with consideration of measurement noise, current injection strength, size of simulated tumors, spatial resolution, and position dependency. The present simulation results are highly promising, demonstrating the high spatial resolution, high accuracy in conductivity reconstruction, and robustness against noise of the proposed algorithm for imaging electrical impedance of a biological system. The present MREIT method may have potential applications to breast cancer imaging and imaging of other organs.     

A low-power,fast-settling reference circuit for high-speed high-resolution ADC

A low-power, fast-settling reference buffer used for high-speed high-resolution ADC is proposed. A replica buffer forms a closed loop to stabilise the operating point and a cascaded gm-boosting technique provides sufficient low output impedance, all of which ensure a high performance for the proposed buffer. The measured results show that the proportion of power consumption by the proposed buffer over ADC is only 2.7%, while settling to 12-bit accuracy within 0.13 ns.     

弹道中段目标平动径向速度估计的状态空间方法

为了分析弹道中段飞行目标的微动分量,需要对雷达回波中的高速平动分量进行准确估计和补偿.该文建立了目标高速平动和微动共同作用下的超宽带信号模型,提出了一种基于状态空间处理的平动径向速度高精度估计方法,该方法可以有效抑制微动分量对平动径向速度估计的影响,估计精度优于传统方法.同时包含高速平动分量和微动分量的超宽带信号模型,也可直接用于后续的微动参数提取处理.仿真结果验证了文中信号模型与径向速度估计方法的有效性.     

面向三维集成封装的硅通孔电特性分析

主要针对三维集成封装中的关键技术之一的硅通孔互连技术进行电性能研究。首先简要介绍了硅通孔互连技术的背景,利用三维全波电磁仿真软件建立地．信号一地TSV模型,对其TDR阻抗和时域TDR／TDT信号进行分析,同时仿真分析了TSV互连线及介质基板所使用的材料和TSV半径、高度、绝缘层厚度等物理尺寸对三维封装中TSV信号传输性能的影响。研究结果可为工程设计提供有力的技术参考,有效地用于改善互连网络的S21,提高三维集成电路系统的性能。