An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

CMOS folding A/D converters with current-mode interpolation

A CMOS folding and interpolating A/D conversion architecture fully compatible with standard digital CMOS technology is described. Fully-differential, continuous-time, current-mode, open-loop analog circuitry is used to achieve high speed. Results from 125 Ms/s 8-b and 150 Ms/s 6-b prototypes implemented in a digital 1 μm n-well CMOS process are presented. The 8-b (6-b) converter occupies 4 mm² (2 mm²) and dissipates 225 mW (55 mW) from a single 5 V power supply     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver

An analog-to-digital converter (ADC) architecture that simultaneously converts two channels is presented. The ADC is intended for use in portable broadband radio receivers that employ in-phase (I) and quadrature (Q) signal paths and will provide an optimal combination of low cost, low power, and high performance. The architecture is pipeline based and employs two separate first stages followed by shared stages for the remainder of the pipeline. A clock generation system for generating all of the required nonoverlapping clock phases is also presented. A prototype ADC with 10 bit resolution and a 40 MHz sample rate that employs the proposed ADC architecture has been fabricated using a 90 nm all-digital CMOS process and occupies an area of 1.727 mm² for a per-channel area of 0.864 mm². The measured performance for the two-channel ADC is a peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) of 58.4 dB and 56.5 dB, respectively, and differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.48/+0.58 LSB and plusmn1 LSB, respectively, with a power dissipation of 50 mW (including analog, digital, and clock generator power) from a 2.5 V supply (1.2 V for the digital section), giving a per-channel power dissipation of 25 mW.     

A 5-V front-end chip for a universal voice-band modem

A circuit that, combined with one or two commercially available digital signal processing (DSP) chips, may implement all voice-band modem standards from 300 b/s to 14.4 kb/s, in full or half duplex operation including echo-cancelling standards, is presented. All analog functions and all non-DSP digital functions are performed by the circuit. Good dynamic range with low distortion in the analog circuitry is maintained while designing for a high-density digital process with high-quality capacitors. Such a process can be used to achieve an area-efficient circuit. The circuit has been implemented in a 1.2-μm CMOS double-poly, double-metal process, operates off a single 5-V supply, and measures only 63 kmil² (40.7 mm²)     

A 12-b, 60-MSample/s cascaded folding and interpolating ADC

This paper describes the analysis, design, and experimental results of a 12-b, 60-MSample/s analog-to-digital converter (ADC). This ADC is based on a cascaded folding and interpolating architecture. The ADC is optimized for digital telecommunication applications. The cascaded folding and interpolating ADC architecture is introduced, optimizing the overall performance of this converter. The integrated track and hold amplifier enables an SNR>66 dB and a THD<72 dB, measured over an analog input signal bandwidth of 70 MHz. The ADC is realized in a 13-GHz, 1-μm BiCMOS process and measures 7 mm² , while dissipating 300 mW from a single 5.0 V supply     

A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering

A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-mum CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 mm² of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 mm² of die area and 0.02 mW of power per tap.     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

A 1.8-V MOSFET-only ΣΔ modulator using substrate biaseddepletion-mode MOS capacitors in series compensation

A low-voltage high-linearity MOSFET-only ΣΔ modulator for speech band applications is presented. The modulator uses substrate biased MOSFETs in the depletion region as capacitors, linearized by a series compensation technique. A second-order fully differential single-loop architecture has been realized in a conventional 0.25-μm digital n-well CMOS process without extra layers for capacitors. An SNDR of 72 dB and an SNR of 77 dB is obtained with 8-kHz signal bandwidth at an oversampling ratio of 64. The circuit consumes about 1 mW from a single 1.8-V power supply and occupies a core area of 0.08 mm²     

A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/Dconverter

This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2×3.1 mm² in a 0.7 μm CMOS process. Several circuit techniques used in this design together with experimental results are presented     

A baseband processor for IS-54 cellular telephony

This paper describes the design of a baseband processor for IS-54 North American cellular telephony standard. The effect of diverse circuit impairments on the error vector in digital mode and on the parasitic amplitude modulation in analog mode are analyzed. An analog offset compensation scheme, which takes advantage of the TDMA operation, is presented. The device incorporates a Manchester data decoder for data transmission in analog mode. The messages can be sent via two interfaces to the DSP or μ-processor. The architecture of the digital signal processing chain is discussed. The device is fabricated in a 0.9 μ CMOS technology with an area of 40 mm²     

A 12-b digital-background-calibrated algorithmic ADC with -90-dBTHD

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate a 12-b algorithmic analog-to-digital converter in the background. At a sampling rate of 125 ksample/s and with monolithic background calibration, the peak signal-to-(noise+distortion) ratio is 71 dB, and the spurious-free dynamic range is 95 dB. The total power dissipation is 16 mW from 5 V. The active area is 5.9 mm² in 1.5-μm CMOS     

CMOS sensors for on-line thermal monitoring of VLSI circuits

The paper presents appropriate sensors for the realization of the design principle of design for thermal testability (DfTT). After a short overview of the available CMOS temperature sensors, a new family of temperature sensors will be presented, developed by the authors especially for the purpose of thermal monitoring of VLSI chips. These sensors are characterized by the very low silicon area of about 0.003-0.02 mm² and the low power consumption (200 μW). The accuracy is in the order of 1°C. Using the frequency-output versions an easy interfacing of digital test circuitry is assured. They can be very easily incorporated into the usual test circuitry, via the boundary-scan architecture. The paper presents measured results obtained by the experimental circuits. The facilities provided by the sensor connected to the boundary-scan test circuitry are also demonstrated experimentally     

A single-chip 5-V 2400-b/s modem

A single-chip split-band 2400-b/s modem has been implemented in a 3-μm CMOS process. A high-level of integration results in a low-cost, high-performance modem. Single-ended analog switched-capacitor circuitry and an application-specific digital signal processor (DSP) combine to perform all modem signal processing. The transmit processing is performed almost entirely in the analog domain. The receiver is performed almost entirely in the analog domain. The IC also supports a number of lower-speed (⩽1200 b/s) split-band modem standards. The chip occupies 68.8 mm² and dissipates 120 mW while operating off a single 5-V supply. System and circuit aspects of the design are discussed, and the measured performance of the IC is summarized     

An analog/digital interface for cellular telephony

This paper describes a mixed-signal ASIC for dual-mode (analog/digital) cellular telephony applications. It consists of two transmit and two receive channels corresponding to the I and Q channels of a quadrature phase-shift keying (QPSK) modulation system. It also includes three 8 b DAC's for control purposes, as well as a bandgap voltage reference and bus interface circuitry. The chip is part of a four-chip implementation of an IS-54 dual mode telephone. The chip was implemented in a 0.8 μm n-well double-metal CMOS process and uses a 5 V power supply. The die area of the chip was 23 mm² and the average power consumption was 125 mW     

A full Nyquist 15 MS/s 8-b differential switched-current A/Dconverter

This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 μm 5 V digital CMOS process and occupies 2.4 mm²      

An adaptive analog noise-predictive decision-feedback equalizer

In this paper, an adaptive noise-predictive decision-feedback equalizer (NPDFE) is presented. The NPDFE architecture and its implementation are described. The NPDFE consists of an analog finite-impulse-response (FIR) forward equalizer, a recursive analog equalizer for noise prediction, and a decision-feedback equalizer (DFE). The recursive equalizer reduces noise enhancement and improves the signal-to-noise ratio (SNR) at the decision slicer input. The prototype targets a magnetic recording channel modeled by a Lorentzian impulse response. Measured results show that compared to a conventional DFE with FIR forward equalizer, the NPDFE achieves a SNR improvement of about 2 dB with PW₅₀=2.5T. The NPDFE consumes 130 mW at a data rate of 100 Mb/s and occupies 1.3 mm² of die area in a 0.5-μm CMOS process     

A high-gain monolithic D-band InP HEMT amplifier

This paper describes a three-stage monolithic amplifier that exhibits a small-signal gain of 30 dB at 140 GHz. The amplifier employs AlInAs/GaInAs/InP high electron mobility transistor devices with 0.1×150 μm² gate periphery, is implemented with coplanar waveguide circuitry fabricated on an InP substrate, and occupies a total area of 2 mm². Gain exceeding 10 dB was measured on-wafer from 129 to 157 GHz. This is the highest reported gain per stage for a transistor amplifier operating at these frequencies     

A second-order double-sampled delta-sigma modulator usingindividual-level averaging

A second-order double-sampled delta-sigma modulator is described. It uses all individual-level-averaging switching scheme to convert capacitor mismatch into high-pass noise. With a sampling rate of 25 MHz and an oversampling ratio of 128, the maximum measured signal-to-noise-and-distortion ratio is 82.2 dB, and the total harmonic distortion is -91.0 dB when the input is 2.5 dB below full scale. The modulator is fully differential, occupies 3.75 mm² in a 1.2-μm CMOS process, and dissipates 25.9 mW (10.2 mW analog and 15.7 mW digital)     

A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driverfor Ethernet and fast Ethernet networking applications

A fast line driver has been developed for networking applications in a 0.4-μ digital CMOS process. It is intended to drive cables with large, low-distortion sinewaves for 10BASE-T and sharp-edged pulses for 100BASE-T-type data communications. The driver has a fully differential architecture and uses a current-feedback approach to achieve small- as well as large-signal closed-loop bandwidths in excess of 100 MHz. It can drive a 10-MHz, 5-V_pp sinewave across a 50-Ω load from a 3.3-V power supply with a total harmonic distortion of -43 dB. The quiescent power consumption of the driver is 25 mW, while its area is 0.15 mm²