基于遗传算法的量子可逆逻辑电路综合方法研究

量子可逆逻辑电路综合主要是研究在给定的量子门和量子电路的约束条件及限制下,找到最小或较小的量子代价实现所需量子逻辑功能的电路。把量子逻辑门的功能用矩阵的数学模型表示,用遗传算法作全局搜索工具,将遗传算法应用于量子可逆逻辑电路综合,是一种全新的可逆逻辑电路综合方法,实现了合成、优化同步进行。四阶量子电路实验已取得了很好的效果,并进一步分析了此方法在高阶量子电路综合问题上的应用前景。     

非可逆逻辑门的量子可逆实现研究

逻辑关系可用逻辑函数表示,量子逻辑关系是可逆的,引入和定义了量子逻辑函数;通过引入辅助量子位,增添量子输出信号的区分位,完成对非可逆逻辑门的改造,使非可逆逻辑门在量子电路中得到可逆实现,并研究了一些有用的非可逆逻辑门的改造方法,给出可实现的优化后的量子电路。     

基于NCV门库的可逆逻辑门进化设计与优化

提出和实现了一种基于遗传算法的可逆逻辑门的设计方法。其特点是预先求出并存储所需功能的可逆逻辑门的真值表,并对NCV基本门库中的控制V门,控制V+门,控制非门,非门进行编码,通过这些基本门的级联,构成染色体暨可逆逻辑门,在逐代进化中按照既定逻辑功能和优化目标进行适应度评估,再利用遗传换代中的选择,交叉,变异等功能进行遗传操作,进而找到功能和性能均符合预定目标的可逆逻辑门。实验结果证明,此方法的可行性、有效性,与传统手工设计可逆逻辑门相比,其在求解速度和能力方面有显著提高。     

基于变换的可逆逻辑电路量子代价优化方法

电路优化是可逆逻辑综合的关键问题。为解决可逆逻辑电路优化算法的复杂度高和可伸缩性差的问题,文中针对常见的以Toffoli为构件的可逆逻辑电路,分析归纳了其中相邻逻辑门的关系,提出了该类电路中子序列的移动和化简规则,进而给出了基于这些规则的可逆逻辑电路优化算法。并在此基础上,提出了利用模板匹配法对已被规则优化的电路进行深度优化的有效方法。通过Benchmark的电路测试,结果表明,该方法能够部分减少可逆电路的门数和控制位数,降低了构建可逆电路的代价。     

综合法研究量子可逆逻辑电路

摘 要：量子可逆逻辑电路优化与综合主要是研究在给定的量子门和量子电路的约束条件下,找到最小或较小的量子代价电路以实现所需电路逻辑功能。量子逻辑真值表综合法是量子电路可逆逻辑综合中最有效的方法之一,它包括正向综合、逆向综合和双向综合。本文推广和定义了横向汉明距离、纵向汉明距离和交叉汉明距离,使用广义汉明距离提出了一种量子电路优化与综合的新方法。研究表明,此方法使量子逻辑电路得到了更好的优化。     

基于改进遗传算法的量子可逆电路综合

针对可逆电路到量子电路的有效映射问题,提出了带禁忌表的大变异自适应遗传算法,用于量子可逆电路的综合.选取量子非门、控制非门、控制V门与控制V+门(NCV)构成量子门库,建立了量子电路计算模型.采用二进制串行编码方案,设计了适应度函数、进化算子及优化规则,实现了带禁忌表大变异自适应遗传算法的量子可逆电路综合,并用Revlib电路库进行了测试.结果表明该综合方法能同时得到多个功能解,且所生成电路的量子代价优于库中电路,验证了提出算法用于量子可逆电路综合的正确性和有效性.     

具有低量子代价的快速可逆逻辑综合方法研究

可逆逻辑是最子计算、低功耗设计和纳米技术领域的关键技术。目前可逆逻辑电路的综合方法效率较低、未能达到区域优化,所以,这些方法仪通用于小璎电路的综合。该文提出了一种基于Davio分解式的综合方法,该方法将逻辑函数转换成对应的正Davio决策图,然后通过对每个图节点模版匹配,最终生成可逆逻辑电路。此方法综合速度快,便于优化,适用于大型电路的综合。     

高效容错可逆的汉明码编码和检测电路

为了检验传输过程中数据的可靠性,设计了容错可逆的汉明码电路。提出了一种新型的可逆逻辑门（FVG）,它是一种四变量奇偶保持门能容错,并且完成了FVG门等价的量子实现。利用FVG 门和现有的容错可逆门,实现了汉明码编码电路和检测电路。以(7,4)汉明码设计为实例,根据量子代价和延迟对其进行性能评估,结果证明该电路比现有电路的性能提高10% ? 20%,仿真实验结果显示,电路逻辑结构正确,性能可靠。     

基于常规逻辑门和原理图方式的可逆逻辑描述

针对可逆逻辑综合在设计较大规模可逆逻辑电路(ALU)时遇到的瓶颈问题。文中借用现行EDA技术的逻辑描述和验证能力,可逆逻辑门的功能表达式为依据,设计具有等功能的常规逻辑组合电路,通过等功能代换的方法,设计实现以常规原理图方式描述的可逆ALU。仿真图中显示的16种运算结果表明,该方法具有一定的可行性和有效性。     

基于输入分解输出匹配的多态自检电路进化设计

针对进化方法在多态自检电路设计方面存在的扩展性问题,该文提出了一种基于输入分解输出匹配的多态自检电路进化设计方法。该方法将原始电路分解为可进化生成部分和固定部分,由此减少待进化设计电路的输入个数以及适应度评价时真值表输入输出组合数量,从而降低电路进化复杂度;在适应度评价阶段,当电路输出位与理想输出匹配度小于1/2时,通过添加非门的形式提高候选电路适应度和种群多样性,防止最优结构的丢失。进化设计实验将多态门和普通门相结合,进行了两种多态自检加法器的设计。结果表明,与传统多态自检电路进化设计方法相比所提方法进化代数分别减少了47.9%和89.1%,单个测试参量下故障覆盖率分别提高了75.7%和79.7%,具有收敛速度快、扩展性好、故障覆盖率高的优点。     

基于二分法量子可逆逻辑电路综合

 为了能以较小的代价自动高效地构造量子可逆逻辑电路,提出了一种新颖的量子可逆逻辑电路综合方法.该方法通过线拓扑变换和对换演算,利用递归思想,将n量子电路综合问题转换成单量子电路综合问题,从而完成电路综合,经过局部优化生成最终电路.该算法综合出全部的3变量可逆函数,未优化时平均需6.41个EGT门,优化后平均只需5.22个EGT门;理论分析表明,综合n量子电路最多只需要n2^n－1个EGT门.与同类算法相比,综合电路所用可逆门的数量大幅减少.同时该算法还避免了时空复杂度太大的问题,便于经典计算机实现.     

基于矩阵编码的量子可逆逻辑电路进化设计方法

 本文研究基于遗传算法的量子可逆逻辑电路综合技术,能实现可逆逻辑电路功能、量子门数、垃圾位数和量子代价的多目标优化设计.建立了量子可逆逻辑电路综合数学模型,采用了量子可逆逻辑电路矩阵编码方案,设计了量子可逆逻辑电路进化操作算子,给出了量子可逆逻辑电路多目标进化设计算法.以8位量子可逆乘法器为设计实例,实验结果证明了所提出的量子可逆逻辑电路多目标进化设计方法是正确有效的.     

Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks

The quantum of power consumption in wireless sensor nodes plays a vital role in power management since more number of functional elements are integrated in a smaller space and operated at very high frequencies. In addition, the variations in the power consumption pave the way for power analysis attacks in which the attacker gains control of the secret parameters involved in the cryptographic implementation embedded in the wireless sensor nodes. Hence, a strong countermeasure is required to provide adequate security in these systems. Traditional digital logic gates are used to build the circuits in wireless sensor nodes and the primary reason for its power consumption is the absence of reversibility property in those gates. These irreversible logic gates consume power as heat due to the loss of per bit information. In order to minimize the power consumption and in turn to circumvent the issues related to power analysis attacks, reversible logic gates can be used in wireless sensor nodes. This shifts the focus from power-hungry irreversible gates to potentially powerful circuits based on controllable quantum systems. Reversible logic gates theoretically consume zero power and have accurate quantum circuit model for practical realization such as quantum computers and implementations based on quantum dot cellular automata. One of the key components in wireless sensor nodes is the cryptographic algorithm implementation which is used to secure the information collected by the sensor nodes. In this work, a novel reversible gate design of 128-bit Advanced Encryption Standard (AES) cryptographic algorithm is presented. The complete structure of AES algorithm is designed by using combinational logic circuits and further they are mapped to reversible logic circuits. The proposed architectures make use of Toffoli family of reversible gates. The performance metrics such as gate count and quantum cost of the proposed designs are rigorously analyzed with respect to the existing designs and are properly tabulated. Our proposed reversible design of AES algorithm shows considerable improvements in the performance metrics when compared to existing designs.     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.     

可逆逻辑表达式的识别和图示方法

可逆逻辑电路是仅包含可逆运算的新型电路,还可根除源于信息损失的能耗和发热,是研究与实现超低功耗集成电路、量子计算机及信息安全等的关键基础。文中针对可逆逻辑电路研究的需要,研究了通过识别可逆逻辑表达式提取可逆逻辑电路结构信息,并加以图形化显示的有效方法和可行算法,以便更形象、直观地表达可逆逻辑电路综合、优化的结果,进而为分析、理解和优化可逆逻辑电路提供方便。     

Design and optimization of buffer chains and logic circuits in aBiCMOS environment

The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied