INL reconstruction of A/D converters via parametric spectral estimation

The work presented in this paper builds on previous research done by the authors in detailing a novel procedure for obtaining a very fast measurement of the integral nonlinearity of an analog-to-digital converter (ADC). The core of the method is the parametric spectral estimation of the ADC output; the static characteristic is subsequently reconstructed as a sum of Chebyshev polynomials, in accordance with a previously developed procedure. The method allows one to test an ADC with sinusoids of any reasonable amplitude (even a slight overdrive is allowed), frequency (no synchronization is needed), and phase (which is digitally compensated). This approach is less accurate than the histogram test but incomparably faster (about 8000 samples are sufficient regardless of the ADC resolution).     

Using sine wave histograms to estimate analog-to-digital converterdynamic error functions

This paper describes a new method for developing analog-to-digital converter (ADC) error function models using modified sinewave histogram methods. The error models may be used to digitally compensate for nonlinearities introduced by the converter. The histogram modification involves sorting of converter output samples based upon an estimated associated input derivative signal. This error model is based upon a previously unpublished result which shows that sinewave histograms yield distinctly different expected errors for each state based upon input signal slope associated with each output sample. This result thus provides a dynamic dependence for expected errors measured by means of histogram methods. Sorted sinewave histograms are used to estimate slope dependent expected errors at each ADC output state (code). The method provides improved error representation by providing error basis functions for every output code. Simulated results prove that this method removes all slope dependent errors for complex ADC architectures while experimental results for an 8-bit 200 MSPS ADC yielded more than 10 dB improvement in spurious-free-dynamic-range (SFDR) over the full Nyquist band. The new method is thus shown to possess wideband dynamic error character     

INL and DNL estimation based on noise for ADC test

This paper presents the linearity characterization of an analog-to-digital converter (ADC). The input signal is noise, which allows low analog area overhead for built-in self-test (BIST). The linearity error estimation is proposed based on the spectral analysis of only the output of the converter. This paper presents the underlying theory and practical results supporting the effectiveness of the proposed method.     

A critical note to IEEE 1057-94 standard on hysteretic ADC dynamictesting

In recent gears, the IEEE 1057-93 Standard (1994) for specifying and testing measurement devices based on analog-to-digital converters (ADCs) earned scientific interest in several topics. In particular, investigations showed the histogram test of the standard to be insensitive to ADC hysteresis. In this paper, an alternative test procedure for determining the dynamic transfer function of an ADC with hysteresis is proposed. The procedure exploits digital signal processing to reduce the large amount of data required by the histogram test. Numerical and experimental results of performance characterization, comparison with a state-of-the-art procedure, and noise-sensitivity analysis are presented and discussed     

Testing an ADC linearized with pseudorandom dither

When a pure sinewave is digitized by an analog-to-digital converter (ADC), the errors are determined by the input voltage and, hence, the phase of the sinewave. The errors generate signal harmonics coherently. One technique used to reduce the harmonic distortion is dithering by combining a pseudorandom wide bandwidth dither signal with the input signal. When pseudorandom dither is added to a sinusoidal signal, it randomizes the ADC errors with respect to the sinewave so that the errors cannot add coherently. The dominant effect of the dither component is to reduce large spurious harmonic distortion components by spreading them into many smaller ones. This paper presents a test method for testing an ADC linearized with pseudorandom dither. We present results of testing a 12-bit, 5 MHz converter and a state-of-the-art, 14-15-bit, 10 MHz converter     

Device Verification Testing of High-Speed Analog-to-Digital Converters in Satellite Communication Systems

This paper presents a step-by-step sequence of operations for the dynamic performance testing of a high-speed analog-to-digital converter (ADC) using on-chip digital demultiplexing and clock distribution. Demultiplexed digital outputs are postprocessed and fed into a computer-aided ADC performance characterization tool. The described methodology reduces test costs and overcomes many test hardware limitations. The problems of high-sampling-rate ADC testing are described. As our focus is on RF communication system applications, we emphasize the measurement of intermodulation distortion (IMD) and effective resolution bandwidth (ERB). Accurate gain and phase matching are also of critical importance. As Fourier analysis is an important component of characterization, we address the issue of automated sample window adjustment to eliminate leakage and false spur generation. A 6-bit 800 MSample/s dual-channel SiGe-based ADC is used as a target example.     

采用预充开关运放的低功耗12位40MS/s流水线模数转换器

设计了一个采用新型预充快速开启开关运放的低功耗12位40MS/s流水线模数转换器(ADC)。该转换器通过采用新型预充开关运放技术、采样保持电路消去结构、动态比较器和优化采样电容,大大降低了电路的功耗。电路设计采用1.8V 1P6M 0.18μmCMOS工艺,仿真结果表明,在40MS/s采样速率下,输入信号为19MHz时,无杂散动态范围(SFDR)为90.15dB,信噪失真比(SNDR)为72.98dB,功耗为27.9mW。     

Noncoherent spectral analysis of ADC using filter Bank

The aim of this paper is to propose a new spectral analysis method for an on-chip analog-to-digital converter (ADC) dynamic test. ADC characterization by spectral analysis has traditionally been done with discrete Fourier transform. This method imposes restrictions to optimize results; one of these is coherent sampling. Recently, some filter structures have been used for spectral analysis of a sinusoidal signal corrupted by harmonics and noise. In this paper, we present a new filter bank structure used for decomposing a signal into its main spectral components. The main application examined is ADC spectral parameter estimation, like signal-to-noise and distortion ratio, signal to noise ratio, total harmonic distortion, and so on, in noncoherent sampling. Computer simulations are used to demonstrate the performance of the proposed filter bank scheme. This structure is a promising built-in self-test (BIST) approach for ADC ICs.     

Experimental Comparison of Different Standards for Dynamic Characterization of ADCs

This paper reports the first results of an experimental comparison of the test procedures described in the IEC and IEEE standards for the measurement of the analog-digital converter (ADC) dynamic performance in the frequency domain. The comparison has been carried out by setting up the standard test benches and applying the standard test procedures for measuring the spurious free dynamic range (SFDR), total harmonic distortion (THD), signal-to-noise-and-distortion ratio (SINAD), signal-to-noise ratio (SNR), and effective number of bits (ENOBs) of the three actual ADCs. The achieved results show a good degree of harmonization, even if the procedures and formulas are different.     

A look-up-table digital predistortion technique for high-voltage power amplifiers in ultrasonic applications

In this paper, we present a digital predistortion technique to improve the linearity and power efficiency of a high-voltage class-AB power amplifier (PA) for ultrasound transmitters. The system is composed of a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and a field-programmable gate array (FPGA) in which the digital predistortion (DPD) algorithm is implemented. The DPD algorithm updates the error, which is the difference between the ideal signal and the attenuated distorted output signal, in the look-up table (LUT) memory during each cycle of a sinusoidal signal using the least-mean-square (LMS) algorithm. On the next signal cycle, the error data are used to equalize the signal with negative harmonic components to cancel the amplifier's nonlinear response. The algorithm also includes a linear interpolation method applied to the windowed sinusoidal signals for the B-mode and Doppler modes. The measurement test bench uses an arbitrary function generator as the DAC to generate the input signal, an oscilloscope as the ADC to capture the output waveform, and software to implement the DPD algorithm. The measurement results show that the proposed system is able to reduce the second-order harmonic distortion (HD2) by 20 dB and the third-order harmonic distortion (HD3) by 14.5 dB, while at the same time improving the power efficiency by 18%.     

A Time-Domain Comparator Based Skipping-Window SAR ADC

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The time-domain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.     

Testing of Precision DAC Using Low-Resolution ADC With Wobbling

Testing of high-resolution, digital-to-analog converters (DACs) with gigahertz clock rates is a challenging problem. The bottleneck is fast and accurate output measurement. This paper presents a novel high-performance DAC testing approach that uses a flash analog-to-digital converter (ADC) to achieve highspeed data acquisition, adopts the wobbling technique to provide a sufficient resolution, and processes the data with a sophisticated algorithm to guarantee high test accuracy. Simulation results show that, by using a 6-bit ADC and wobbling, the static linearity of 14-bit DACs can be tested to better than 1-LSB accuracy. The experimental results that are included in the paper also affirm the performance of the algorithm. This method provides a solution to both the production and on-chip testing problems of high-performance DACs.     

一种新型的大动态范围CCD相机视频信号处理电路

由于目前的CCD尤其科学级CCD的动态范围高达105:1,甚至106:1,此时若要满足ADC的动态范围大于CCD相机的动态范围,则必须选择分辨力为18～20bit的ADC,而航天级或高等级的高分辨力ADC较少且价格昂贵。本文利用CCD相机系统的噪声谱密度跟信号大小有密切关系这一特点,对于强光信号和弱光信号采用不同的信号处理链,从系统通道增益的角度阐述了低分辨力ADC实现高分辨力模数转换的原理及硬件实现方案,最后通过实验室成像测试验证,实验结果表明,用低分辨力A/D转换器采用粗细量化相结合方式实现了高分辨力模数转换,并提高了CCD相机的动态范围。     

An FFT-based method to evaluate and compensate gain and offset errors of interleaved ADC systems

Interleaved analog-digital converter (ADC) systems can be used to increase the sampling rate for a given ADC implementation technique. In theory, the maximum sampling rate that can be achieved is limited only by the bandwidth and the practical limits related to the power and space of integrated circuits. In this paper, a solution to increase the sampling rate of a digitizing system based on interleaved ADCs is presented. An error analysis, which takes into consideration offset and gain errors of the different ADC channels, is performed in order to quantify the effect of such errors in the system's performance. A software method based on the fast Fourier transform is presented for offset and gain error compensation of interleaved ADC associations. Numerical simulations and experimental results are used to validate the theory and the proposed compensation algorithm.     

The Histogram Test of ADCs With Sinusoidal Stimulus Is Unbiased by Phase Noise

This paper intends to show that the presence of normally distributed phase noise or jitter in the test setup or in the analog-to-digital converter (ADC) itself does not cause a bias in the sinusoidal histogram test estimation of the transfer function of an ADC. The analytical proof presented demonstrates that there is no need to use an extra overdrive when stimulating the ADC, as is the case with amplitude noise.     

Analysis of the Residual Spectrum in ADC Dynamic Testing

This paper presents a procedure that derives the estimation of the significant components in the residual spectrum in analog-to-digital converter (ADC) dynamic testing. The method for emulating coherent sampling by the interpolation of the discrete Fourier transform (DFT) to estimate the frequency, amplitude, and phase of the particular residual component is described. Analysis has been done on the components below the level of the quantization resolution. The procedure for threshold estimation for distinguishing between significant components and the noise floor is provided.      

Jitter Measurement and Compensation for Analog-to-Digital Converters

Clock jitter is measured and digitized by a stochastic time-to-digital converter (TDC). This jitter information is used to compensate the sampling error of an analog-to-digital converter (ADC) caused by the clock jitter. The following two system scenarios are covered: 1) an ADC with a clean external clock and 2) an ADC with an external clock as the main jitter source. TDC calibrations for both scenarios are proposed. The calibrations are based on signal reconstruction and can be performed in the background. Both theoretical analyses and system simulations are provided to verify the proposed jitter compensation and TDC calibration techniques.      

Analysis of second-order harmonic distortion of ADC usingbispectrum

This paper presents a new frequency-domain approach to test the second-order harmonic distortion of an analog-to-digital converter (ADC). It uses triple correlation and its Fourier transform, bispectrum, to suppress quantization noise and improve the testing accuracy of weak second-order harmonics. Our approach is independent of the triggering delay that is a known weakness of the spectral averaging method. The new method is also less sensitive to the quantization noise than the power spectrum averaging method. Both theoretical analyses and illustrative computer simulations are provided     

High Precision SAR ADC Using CNTFET for Internet of Things

A high precision 10-bit successive approximation register analog to digital converter (ADC) designed and implemented in 32nm CNTFET process technology at the supply of 0.6V, with 73.24 dB SNDR at a sampling rate of 640 MS/s with the average power consumption of 120.2 μW for the Internet of things node. The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction logic. These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and noise level are within the limit. The proposed architecture has high scalability to CNTFET technology and also has higher energy efficiency. We compared the results of CNTFET based SAR ADC with other known architectures and confirm that this proposed SAR ADC can provide higher precision, power efficiency to the Internet of things node.     

莱斯信道下大规模MIMO系统混合模数转换器的随机向量量化方案

针对大规模MIMO系统用配置单精度模数转换器(ADC)来降低系统能耗会导致系统损失部分性能的问题,提出了一种莱斯信道下大规模MIMO系统的采用混合ADC的随机向量量化(RVQ)改进方案。该方案在频分双工模式下,首先在基站端采用高分辨率ADC和低分辨率ADC混合的接收方案处理信号,使接收的导频信号和有用信号具有较高的转换精度;系统对导频信号进行信道估计后,再对信道状态信息(CSI)进行RVQ处理,以此减小系统的反馈开销;最后运用最小均方误差(MMSE)信号检测算法减轻由量化误差引起的的用户间干扰,从而达到降低能耗并减小系统性能损失的目的。实验结果表明,这种改进的RVQ方案能在降低系统能耗的基础上有效减小系统容量损失,并使其和速率接近传统的高分辨率ADC接收方案。