0.8 μW 12-bit SAR ADC sensors interface for RFID applications

The design and first measuring results of an ultra-low power 12 bit successive-approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for low power consumption. The power consumption is 0.52 μW from a 1.2 V supply with a sample clock of 3.125 kHz and 0.85 μW at 6.25 kHz. This gives 136 pJ per conversion or 66 fJ per conversion step. As per authors’ knowledge, 66 fJ per conversion step is the best reported so far.The ADC was realised in the NXP CMOS 0.14 μm technology; the area was 0.35 mm². Only four metal layers were used in order to allow 3D integration of the sensors.     

A 1.2?V 8-bit 1 MS/s SAR ADC with Res–Cap segment DAC for temperature sensor in LTE

A 1.2?V 8-bit single ended successive approximation register analog-to-digital converter (ADC) for long term evolution (LTE) system is implemented. A novel 5-bit resistor and 3-bit capacitor segment digital-to-analog converter is used to minimize the chip area and reduce the product cost. A rail-to-rail amplifier is used as the pre-amplifier of the comparator in order to obtain the full input swing and the adequate gain for low supply. The offset voltage of the comparator is below 2?mV from the Monte Carlo simulated results. The ring oscillator, current generator and bandgap are integrated into the ADC to satisfy multiple applications. The serial peripheral interface is used to adjust the sampling frequency and the key block??s bias current in order to change the dynamic and static power consumption to satisfy the different need in LTE?? modules. The design was fabricated in a 0.13???m CMOS process with an area of 0.1?mm² and a power of 1.2 mW. The measurement results show that the differential nonlinearity and integral nonlinearity of the proposed ADC are +0.11/?0.18 LSB and +0.8/?0.04 LSB, respectively. The spurious free dynamic range and signal-to-noise distortion ratio can get 53 and 43.3?dB, respectively.     

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

We present a new noise shaping method and a dual-polarity calibration technique suited for successive approximation register type analog to digital converters (SAR–ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR–ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3 μW power with 1.8 V supply.     

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme

This paper presents a low-power 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a novel energy-efficient capacitor-switching scheme. Compared to the conventional scheme, the proposed split-capacitor V_cm-based capacitor-switching scheme can reduce the capacitor-switching energy by about 92% with better monotonicity. Meanwhile, full-custom SAR logic and registers, variable-delay self-timing cell and dynamic comparator with proposed two-segment DC offset correction scheme are also implemented to improve the conversion speed and accuracy requirements. The prototype was fabricated in 65-nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2 dB, while consuming 960 μW from 1.2 V supply voltage. The figure of merit (FoM) is 36.8 fJ/conversion-step and the total active area is only 220×220 μm².     

Calibration algorithm for 16-bit voltage-mode R–2R DAC

A novel calibration algorithm is presented for the 16-bit voltage-mode R–2R Digital-to-Analog converter (DAC). The proposed calibration can be realized with only some digital circuits and an additional calibrating DAC (CaliDAC) identical to the main DAC (MDAC) added. With the weighing-coefficient compressing technology (WCT) adopted, the nonlinearity of the CaliDAC can be compressed when the calibration is implemented, therefore leaving almost no effect on the output. Adopting the segment-calibration technology (SCT), the integral nonlinearity (INL) errors of the output can be calibrated segment by segment. With the proposed calibration algorithm, the INL errors in the final output can be calibrated successfully in the range of [−0.5LSB, 0.5LSB] for 16-bit voltage-mode R–2R DAC.     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

A 12-bit 100 MS/s pipelined SAR ADC with addition-only digital error correction

A new redundant successive approximation register (SAR) ADC architecture with digital error correction is presented to avoid the comparator offset issue and subtraction operations. A 2-channel 12-bit 100 MS/s SAR ADCs based on the proposed architecture with voltage-controlled delay lines based time-domain comparator is designed in a 65 nm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.81 dB (11.47 ENOB), a spurious free dynamic range (SFDR) of 80.33 dB for a near Nyquist input at 100 MS/s, while dissipating 11 mW from a 1.2-V supply, giving a FOM of 38.8 fJ/Conversion-step.     

A novel node selection scheme for energy-efficient cooperative spectrum sensing using D–S theory

Wireless Networks - Energy-efficient and reliable detection of available spectrum are fundamental objectives for cooperative spectrum sensing (CSS) in cognitive radio sensor networks (CRSNs). In...     

采用SAR结构的8通道12位ADC设计

本文设计实现了一个8通道12位逐次逼近型ADC。转换器内部集成了多路复用器、并/串转换寄存器和复合型DAC,实现了数字位的串行输出。整体电路采用HSPICE进行仿真,转换速率为133KSPS,转换时间为7.5μs。通过低功耗设计,工作电流降低为2.8mA。芯片基于0.6μmBiCMOS工艺完成版图设计,版图面积为2.5×2.2mm2。     

Microconsuming 8–12 GHz GaN Power Amplifiers

Russian Microelectronics - This paper describes a cascade circuit of a gallium nitride (GaN) power amplifier whose chip area is smaller by factors of 4 to 6 than that of traditional amplifiers on...     

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.     

Rate–distortion optimization of multi-exposure image coding for high dynamic range image coding

High dynamic range (HDR) images have many practical applications because they offer an extended dynamic range and a more realistic visual experience. A HDR image is usually stored in floating-point format, so pre-processing is required to make the HDR image compatible with coding standards. A transfer function is also used to achieve better coding efficiency. Typically, HDR images are generated using several low dynamic range (LDR) images with different exposures. Instead of compressing the HDR image when it is generated from images with multiple exposures, this study proposes a technique to compress the multi-exposure images. The HDR image generation, as well as the multi-exposure images fusion, can be realized in the decoder. The proposed framework encodes the multi-exposure images using MV-HEVC where the inter-view redundancy is well exploited when an accurate intensity-mapping function between the multi-exposure images has been established. Multi-exposure image coding is used to produce a high-quality HDR image so the rate–distortion optimization (RDO) is modified by considering both the reconstruction quality of the current block and its effect on the multi-exposure fused image. A Lagrange multiplier is modified to maintain a balance between the rate and the modified distortion during the RDO process. Compared to encoding the generated HDR image using HEVC range extension, the experimental results show that the proposed technique achieves significant bitrate savings for equivalent quality in terms of HDR-VDP-2.     

Dual Role of Cu-Chalcogenide as Hole-Transporting Layer and Interface Passivator for p–i–n Architecture Perovskite Solar Cell

Inorganic hole-transport layers (HTLs) are widely investigated in perovskite solar cells (PSCs) due to their superior stability compared to the organic HTLs. However, in p–i–n architecture when these inorganic HTLs are deposited before the perovskite, it forms a suboptimal interface quality for the crystallization of perovskite, which reduces device stability, causes recombination, and limits the power conversion efficiency of the device. The incorporation of an appropriate functional group such as sulfur-terminated surface on the HTL can enhance the interface quality due to its interaction with perovskite during the crystallization process. In this work, a bifunctional Al-doped CuS film is wet-deposited as HTL in p–i–n architecture PSC, which besides acting as an HTL also improves the crystallization of perovskite at the interface. Urbach energy and light intensity versus open-circuit voltage characterization suggest the formation of a better-quality interface in the sulfide HTL–perovskite heterojunction. The degradation behavior of the sulfide-HTL-based perovskite devices is studied, where it can be observed that after 2 weeks of storage in a controlled environment, the devices retain close to 95% of their initial efficiency.     

Efficient primal–dual fixed point algorithms with dynamic stepsize for composite convex optimization problems

Multidimensional Systems and Signal Processing - In this paper, we propose a new primal–dual fixed point algorithm with dynamic stepsize ( $$hbox {PDFP}^{2}O_{DS_{n}}$$ ) for solving convex...     

An efficient rate–distortion optimization method for dependent view in MV-HEVC based on inter-view dependency

Rate–distortion optimization (RDO) is utilized to select the optimal coding parameters in multi-view video coding (MVC), which employs a Lagrange multiplier to balance the relationship between the distortion and the bitrate. In this paper, an efficient RDO method for the dependent view (DV) in multi-view video (MVV) is proposed based on inter-view dependency. First of all, by investigating the sources of the distortion in the DV, a new distortion model for the DV is established. In addition, based on the proposed distortion model, an efficient Lagrangian multiplier decision for B frame is proposed by considering the inter-view dependency. Finally, the optimized Lagrangian multiplier for P frame is designed using the scaling factor which is deduced to have a linear relationship with the disparity between I frame and P frame. Experiment results demonstrate that compared with the original HTM-16.0 encoder, the proposed overall method reduces 12.19% BD-rate for the DV on average, bringing 0.40 dB BD-PSNR gain.     

A CMOS VCO Architecture Suitable for Sub-1 Volt High-Frequency (8.7–10 GHz) RF Applications

This paper proposes an LC-based oscillator structure which enables operation from a supply voltage as low as 0.85 V, while being suitable for high-frequency RF applications. Two VCO prototypes were fabricated in a standard 0.18 m CMOS process. The 8.7 GHz VCO operates from a supply voltage of 0.85 V, consumes 6 mW, and exhibits –100 dBc/Hz phase noise at 600 kHz offset. The 10 GHz prototype operates from a supply voltage of 1 V, consumes 9 mW, and has –98 dBc/Hz phase noise at 600 kHz offset. A tuning range of 400–450 MHz is achieved without using varactors.     

An improved method for the design of quadrature mirror filter banks using the Levenberg–Marquardt optimization

This paper presents an improved and efficient method for the design of a two-channel quadrature mirror filter (QMF) bank. In the proposed method, the filter bank design problem is formulated as a low-pass prototype filter design problem, whose responses in the passband and stopband are ideal and their filter coefficients value at quadrature frequency is 0.707. A new method is developed for the design of a low-pass prototype filter which minimizes the objective function by optimizing the filter taps weights using the Levenberg–Marquardt method. When compared with other existing algorithms, it significantly reduces peak reconstruction error (PRE), error in passband, stopband and transition band. Several design examples are included to show the increased efficiency and the flexibility of the proposed method over existing methods. An application of this method is considered in the area of subband coding of the ultrasound images.