Blind equalization of time errors in a time-interleaved ADC system

To significantly increase the sampling rate of an analog-to-digital converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the time mismatch errors. The estimation method requires no knowledge about the input signal, except that it should be band limited to the foldover frequency /spl pi//T/sub s/ for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the time errors. The Cramer-Rao bound (CRB) for the time error estimates is also calculated and compared to Monte Carlo simulations. The estimation method has also been validated on measurements from a real time-interleaved ADC system with 16 ADCs.     

Analysis of mismatch effects in a randomly interleaved A/D converter system

Time interleaving can be used to significantly increase the sampling rate of an ADC system. However, the problem with time interleaving is that the ADCs are not exactly identical. This means that time, gain and offset mismatch errors are introduced in the ADC system, which cause nonharmonic distortion in the sampled signal. One way to decrease the impact of the mismatch errors is to spread the distortion over a wider frequency range by randomizing the order in which the ADCs are used in the interleaved structure. In this paper we analyze how the spectrum is affected by mismatch errors in a randomly interleaved ADC system. We also discuss how the mismatch errors can be estimated.     

Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators

We propose a digital background adaptive calibration technique for correcting offset and gain mismatches in time-interleaved multipath analog-digital (A/D) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is also effective for any other time-interleaved A/D converter topology. Simulation results on a high-performance four-path bandpass /spl Sigma//spl Delta/ modulator, operating on a 5-MHz band at a clock frequency of 320 MHz, demonstrate the effectiveness of the proposed calibration technique, which allows us to achieve significant improvements of the signal-to-noise ratio and the spurious-free dynamic range in the presence of mismatches.     

Blind detection of equalization errors in communication systems

In adaptive channel equalization, transmitted symbol estimates at the equalizer output may be in error because of excessive channel noise, convergence of the equalizer to a “closed-eye” local minimum, or error propagation if the equalizer has a decision feedback structure. This paper is concerned with the detection of equalization errors (i.e., errors in transmitted symbol estimates) in a blindfolded manner whereby no direct access to the channel input is required. The detection problem is cast into a binary hypothesis testing framework. Assuming a linear communication channel that is time-invariant during the test interval, a relationship between the presence of equalization errors and time variations in the underlying linear model taking the transmitted symbol estimates to the equalizer input is established. Based on this relationship, a uniformly most powerful test is constructed to detect the presence of equalization errors in finite-length observations. Finite sample size and asymptotic detection performance of the test is studied. A method for estimating the equalization delay without direct access to the channel input is developed. The effectiveness of the test is illustrated by way of computer simulations     

A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

GaAs photoconductive switches have been integrated with two parallel 4-bit CMOS analog-to-digital (A/D) converter channels to demonstrate the time-interleaved sampling of wideband signals. The picosecond sampling aperture provided by low-temperature-grown-GaAs metal-semiconductor-metal switches, in combination with low-jitter short-pulse lasers, enables the optically-triggered sampling of electrical signals with tens of gigahertz bandwidth at low to medium resolution. A pair of parallel sampling paths, one for sampling and the second for feedthrough cancellation, generate a differential held signal that is quantized by a low-input capacitance, high-speed flash A/D converter. Dynamic offset averaging is employed to improve converter linearity. An experimental time-interleaved two-channel A/D converter provides about 3.5 effective bits of resolution for inputs up to 40 GHz when tested at an optically-triggered sampling rate of 160 MHz. The sampling rate was limited by the available optical source. Each A/D converter channel operates up to a 640-MHz conversion rate, dissipates 70 mW of power, and occupies an area of 150 /spl mu/m /spl times/ 450 /spl mu/m in a 2.5-V, 0.25-/spl mu/m CMOS technology.     

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.     

双通道时间交织ADC采样系统的频域纠正补偿

针对双通道时间交织模数转换器（ ADC )采样系统中的通道间失配问题,提出了一种新的频域纠正补偿算法,即利用单次测量得到的不同频率处的固定补偿系数来实现时间交织ADC频响的部分补偿,并从理论和实验上分别进行了推导和可行性验证。实验结果表明：在双通道12比特2 Gsample/s时间交织ADC采样系统下,650 MHz带宽范围内的无杂散动态范围（ SFDR)可以提高到40 dB。     

Decorrelating compensation scheme for coefficient errors of a filter bank parallel A/D converter

In this letter, a parallel analog-digital (A/D) conversion scheme with a filter bank for low intermediate-frequency receivers is presented. The analysis filters of the filter bank divide the frequency components of the received signal, and achieve parallel A/D conversion. Therefore, the required conversion rates and the resolution of the A/D converters can be reduced and the receiver can demodulate wideband signals. As the analysis filters consist of analog components, their coefficients include errors. These errors cause mutual interference between signals in orthogonal frequencies. In order to remove this interference, a decorrelating compensation scheme is proposed.     

高精度模数转换器在压力信号采集系统中的应用

本文设计的压力信号采集系统采用了高精度24位的模数转换器ADS1255.如何使用这种高性能的模数转换器,本文给出了硬件和软件设计方法并作了详细的说明.本文使用的模数转换器硬件精度高,接口简单,通用性强.使用这种高精度模数转换器的压力信号采集系统稳定可靠,已通过了井下试验的测试,满足采集井底压力信号的要求.     

多通道时域交织逐次逼近型模数转换器通道失配建模

时域交织ADC由多个独立的ADC构成,这种并行处理数据的方式可以达到很高的采样率。子通道采用SAR ADC可实现低功耗并保持很好的线性度。但是,这种结构受到三种失配的影响：失调失配,增益失配和采样时刻偏差。本文从频域分析出发,重点研究了在通道数目较多的情况下失配对TI SAR ADC性能的影响,此外,推导得出M通道交织ADC的DNL和INL的均方根值是单通道ADC均方根值的1/√M。最后通过Matlab仿真验证了推导出的公式。这些公式可以为设计TI ADC时确定失配范围提供参考,并为提出校准算法提供思路。     

Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter

Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (ADCs). This paper focuses on the sample-time error. Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented.     

高速A/D转换器的选择--在选择A/D变换器时,其应用场合是一条重要的依据

模数转换器是连接模拟和数字世界的一个重要接口.A/D转换器将现实世界的模拟信号变换成数字位流以进行处理、传输及其他操作.     

A/D和D/A转换器IC

代码转换器提高DSP效率 TLV320AIC10 16位代码转换器提供连续数据传输,可支持DSP自动缓冲单元,减少因缓冲(最高达64kB)不足而引起的中断。该器件特性有每秒22k的采样速率,一个串行接口,增益范围为-36～24dB的可编程增益放大器,一个2:1模拟多路复用器,以及节能备用模式。其它性能包括:工作电压3～5.5V,在采样速率为每秒8k时功耗为39mW。     

A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.     

联合多脉冲检测的PSWF正交调制信号盲自适应均衡

卫星通信信道的复杂时变特性,使基于椭圆球面波函数(Prolate Spheroidal Wave Function,PSWF)的正交调制信号脉冲组的正交性受到破坏,已有均衡方法未能充分利用多脉冲干扰中的有用信息,效果有限。针对该问题,结合信道均衡与多脉冲检测各自的优势,提出一种联合多脉冲检测的PSWF时域正交调制信号自适应均衡方法,利用多脉冲检测消除脉冲间干扰的能力,降低均衡模块的阶数及算法难度;同时,利用均衡模块对信道的部分补偿作用,为多脉冲检测改善信道环境。在相同信道条件下,所提方法获得同等量级误比特率所需信噪比较自适应判决反馈均衡算法降低约2 dB。     

Current-mode A/D converter

The authors report the design of a new current-mode A/D converter, based on a modified successive-approximations model, in 1.2 μm CMOS technology. The proposed circuit is characterised by good accuracy and fast dynamic performance, low power consumption and small occupation area. SPICE simulations allow the design approach to be validated and the electrical performance of the ADC to be predicted     

LMS calibration of sampling timing for time-interleaved A/D converters

Novel sampling-timing calibration for time-interleaved A/D converters is proposed and verified by simulation. An FIR-filter structure exploiting the sampling theorem provides a simple but accurate time derivative of the converted signal and hence enables reliable estimation and compensation of sampling-time deviation of each unit ADC assisted by a reference converter and an LMS algorithm.     

Blind adaptive joint multiuser detection and equalization in dispersive differentially encoded CDMA channels

The problem of blind adaptive joint multiuser detection and equalization in direct-sequence code division multiple access (DS/CDMA) systems operating over fading dispersive channels is considered. A blind and code-aided detection algorithm is proposed, i.e., the procedure requires knowledge of neither the interfering users' parameters (spreading codes, timing offsets, and propagation channels), nor the timing and channel impulse response of the user of interest but only of its spreading code. The proposed structure is a two-stage one: the first stage is aimed at suppressing the multiuser interference, whereas the second-stage performs channel estimation and data detection. Special attention is paid to theoretical issues concerning the design of the interference blocking stage and, in particular, to the development of general conditions to prevent signal cancellation under vanishingly small noise. A statistical analysis of the proposed system is also presented, showing that it incurs a very limited loss with respect to the nonblind minimum mean square error detector, outperforms other previously known blind systems, and is near-far resistant. A major advantage of the new structure is that it admits an adaptive implementation with quadratic (in the processing gain) computational complexity. This adaptive algorithm, which couples a recursive-least-squares estimation of the blocking matrix and subspace tracking techniques, achieves effective steady-state performance.     

A low-power inverted ladder D/a converter

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-/spl mu/m, 3.3-V implementation consuming 22-/spl mu/A current with output resistance of 40 k/spl Omega/ and effective parasitic capacitance of 650 fF.     

A low-complexity digital background calibration of sample-time error in time-interleaved A/D converters

A digital background calibration technique to estimate the sample-time error (timing-skew) in time-interleaved ADCs is presented. Compared to the state-of-the-art, this technique requires a simpler digital block and, hence, a lower power dissipation. The proposed technique detects timing skew for each channel by means of finding zero-crossing samples with respect to a reference comparator. Simulation results show that it can effectively correct timing errors for any type of input signal up to Nyquist, and achieves a high convergence speed with a very low computational complexity.