All-optical 40 Gbit/s XOR gate with dual ultrafast nonlinear interferometer

A novel XOR logic gate using dual cascaded ultrafast nonlinear interferometer elements based on semiconductor optical amplifiers is proposed and demonstrated at 40 Gbit/s. The gate is switched at the line rate rather than twice line rate, as in previously reported differential XOR gates.     

40 Gbit/s全光异或门性能仿真

为了提高基于SOA-MZI结构的全光异或门的输出消光比,优化系统性能,将SOA和HNLF相结合,在光通信系统设计软件OptiSystem7.0仿真平台上搭建了基于SOA-MZI的全光异或仿真实验模型,对两路40 Gbit/s的RZ码数据信号进行了全光异或仿真实验。利用HNLF的非线性效应设计了一种优化结构对基于SOA-MZI的全光异或输出信号进行优化,并对优化前后的信号时域波形图和系统眼图进行了比较分析,通过多次反复实验得到一组最佳的系统参数,使得基于SOA-MZI的全光异或门的输出消光比从10 dB提高到约28 dB。实验结果表明:常规的基于SOA-MZI的全光异或门由于相消干涉不彻底造成输出消光比较低,而经过优化,很好地解决了这种问题,提高了异或输出消光比,优化了系统性能。     

2 Gbit/s regenerator using commercial silicon bipolar circuits

A regenerator for fibre optic systems which operates at 2 Gbit/s has been demonstrated using commercially available silicon bipolar integrated circuits. A parallel processing technique with following interleaver is used to achieve the required decision gate function. The regenerator has an ?2 mV front end sensitivity for a<1 in 109 BER with a 215?1 PRBS.     

24 Gbit/s regenerating demultiplexer IC in silicon bipolar technology

A 1:2 regenerating demultiplexer IC has been realised in an advanced self-aligned silicon bipolar technology using 0.8 mu m lithography. The circuit can be operated up to 24 Gbit/s at 5 V supply voltage. This is by far the highest data rate reported for a demultiplexer in any IC technology.<>     

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ atV_{CE} = 1V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.     

Submicron silicon bipolar master-slave D-type flip-flop for use as 8.1 Gbit/s decision circuit and 11.2 Gbit/s demultiplexer

The authors have designed and implemented a submicron silicon bipolar master-slave D-type flip-flop integrated circuit which can be used either as a decision circuit or a demultiplexer, operating at data rates as high as 8.1 and 11.2 Gbit/s, respectively. The circuit was fabricated using a 0.6 mu m, nonpolysilicon emitter technology, occupying an area of 0.8 mm*0.9 mm, and dissipating 410 mW of power.<>     

15 Gbit/s silicon bipolar amplifier IC using a novel mountingtechnique

A DC-coupled silicon bipolar amplifier IC, for operation in future multigigabit optical communication systems, has been fabricated using ⩾30 GHz double-polysilicon transistors. Using a novel HF connection technique for reducing the bondwire inductance, we have succeeded in the fabrication of a 14 dB gain amplifier IC, with a flatness better than ±0.5 dB, combined with a -3 dB bandwidth of 12.8 GHz. This is the highest bandwidth ever reported for a bonded amplifier circuit in any semiconductor technology     

11.4 Gbit/s silicon bipolar multiplexer IC employing 2 mu m lithography transistors

A very high-speed 2:1 multiplexer IC operating up to 11.4 Gbit/s has been implemented. The circuit was fabricated using a 12 GHz non-polysilicon-emitter self-aligning bipolar process with 2 mu m lithography. Despite realisation in a relatively simple technology, this is the highest operating speed yet achieved with any technology.<>     

Integrator circuit with bipolar transistor for Gbit/s applications

A novel continuous time integrator circuit suitable for Gbit/s signal processing is presented. It takes advantage of the inherent low impedance characteristic of broadband transistors. Instead of charging a capacitor from a high impedance current source, basically an inductance is used which is driven by a low impedance voltage source.<>     

40 Gbit/s silicon optical modulator for highspeed applications

A high-speed silicon optical modulator based on the free carrier plasma dispersion effect is presented. It is based on carrier depletion of a pn diode embedded inside a silicon-on-insulator waveguide. To achieve high-speed performance, a travelling-wave design is used to allow co-propagation of the electrical and optical signals along the length of the device. The resulting modulator has a 3 dB bandwidth of ~30 GHz and can transmit data up to 40 Gbit/s.     

10 Gbit/s AND gate using dual-gate GaAs MESFET

Using a commercial dual-gate GaAs MESFET transistor mounted in a microstrip circuit, an AND gate has been built. With the 100 ps (FWHM) wide test pulses available, a speed of 10 Gbit/s NRZ and a pulse suppression of at least 14 dB was obtained.     

Dual-in-line laser diode module for fiber-optic transmission up to 4 Gbit/s

A very high-speed laser diode (LD) module, having a "butterfly" type dual-in-line structure is developed. This LD module consists of a laser diode, a p-i-n-photodiode for monitoring the laser power, a thermoelectric cooler, and a thermistor. The power emitted from the LD is coupled into a single-mode fiber using a hemispherical tapered fiber technique. The microwave design of the LD module employing high frequency equivalent circuit and scattering (S) parameters is shown. Parasitic inductances and capacitances in the LD module degrade the high frequency characteristics. This is a very serious problem in gigabit fiber-optic transmission systems. The microwave impedance, small signal high frequency characteristics, and high-speed pulse response of the fabricated module with low parasitics are also shown. Electrical resonance frequency is 4.8 GHz and well opened eye patterns up to 4 Gbit/s are obtained in the experiments.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

Dispersion-free single-mode fibre transmission experiments up to 1.6 Gbit/s

Long-span single-mode fibre transmission experiments at 1.3 ?m have been refined toward higher digit rate and longer fibre span. Error-rate against receiving optical level characteristics showed that optical power penalties at 100 Mbit/s, 1.2 Gbit/s and 1.6 Gbit/s are negligible, even after 30 km, 23 km and 13 km fibre transmission, respectively.     

Silicon bipolar laser and line driver IC with symmetrical output pulse shape operating up to 12 Gbit/s

A silicon bipolar laser and line driver IC with an outstanding symmetry of the (single-ended) output pulse shape is presented. The pulse shape can be optimally adjusted via only two external potentiometers, independent of operating speed and output current range. The circuit, fabricated in a 0.8 mu m self aligned double-polysilicon technology, operates up to 12 Gbit/s.<>     

Demonstration of 20 Gbit/s all-optical logic XOR in integratedSOA-based interferometric wavelength converter

The results of optical logic exclusive-OR (XOR) at up to 20 Gbit/s in an integrated SOA-based Mach-Zehnder interferometer are presented. For the first time, to the knowledge of the authors, BER measurements are demonstrated on 10 Gbit/s optical logic XOR, with zero penalty. In addition. For the first time 20 Gbit/s all-optical XOR, with an integrated device that allows simple, stable, and efficient operation, is demonstrated     

Low power optical gate HBT driver array for 2.5 Gbit/s ATMswitching

A four element driver array for optical gates in a 2.5 Gbit/s optical ATM switch is presented. The circuit uses a GaAs-GaAlAs heterojunction bipolar transistor (HBT) technology. It enables a switching time of <300 ps and current up to 150 mA with <400 mW per gate power consumption     

10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively     

Silicon bipolar IC for PRBS testing generates adjustable bit ratesup to 25 Gbit/s

For the first time, a completely integrated pseudo-random pattern generator providing adjustable bit rates up to at least 25 Gbit/s without additional external multiplexing is presented. The sequence length is 2ⁿ-1. The application of the monolithic Si bipolar IC serves as a single chip measurement instrument for pseudo-random binary sequence (PRBS) generation required for the characterisation and development of high-speed components used in future optical fibre communication systems. Only three external microwave components are needed for operation: a clock generator, a power divider and a phase shifter. The chip is realised in an advanced implanted base silicon bipolar technology