长脉冲532nm激光器对静脉血管的封闭效应

Laser treatment represents an attractive option to other methods of vessel diseases especially varicose veins. A long pulse (30-50ms) 532nm laser was used in our experiments, with the pulse duration matching the thermal relaxation time of the vessels and the green laser matching the absorption spectrum peak of the blood.Laser irradiates nude vein vessels directly or exterior skin to finish operation faster and to acquire the practical data for upper enteron varicose vein treatment in several animal experiments performed in vivo. The 5Jenergy pulse allows us to finely occlude rabbit or dog‘s vein vessels up to 2 mm in diameter when irradiating them off external skin. Blood vessels are occluded at once, and later biopsy specimens show the immediate and long-term lasting occlusion effect. While vessels are irradiated directly, they are usually irradiated to perforate, detailed causes are still under investigation. Animal experiments showed that the long pulse green laser therapy is a safe and effective solution to the vein‘s occlusion, which promises such laser with high energy of each pulse and 30-50 ms duration is an ideal candidate for vessel diseases treatment.     

激光定位深亚微米CMOS SRAM单粒子翻转敏感区

The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18/zm CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.     

MOSFET-Iike CNFET based logic gate library for low-power application： a comparative study

The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

A Systematical Approach for Noise in CMOS LNA

A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5.2GHz CMOS LNA.     

Forming of Very Shallow Junction for S/D Extension in Deep Sub-Micron CMOS Devices

Very shallow junctions for S/D extension in deep sub\|micron CMOS devices are required to suppress the short channel effect as devices scaling down,and the surface concentrations ( N s) of these junctions need to be kept in a higher value to reduce the series resistance of the lightly doped drain structure.But it is very difficult for the conventional ion implantation to meet the requirement above.This article presents the results of forming very shallow and ultra\|shallow junctions used in 0.25 micron ...     

Numerical Simulation of Pulse Shortening in RBWOs

Pulse shortening hinders improvement of microwave output energy for high power microwave tubes. So far, it is also an unresolved problem in the field of high power microwave devices.In this paper, relativistic backward wave tube (RBWO) is treated as an example to study the pulse shortening phenomena. The influences of gas existing in the tube and explosive emission in inner surface of RBWO are all investigated by means of the particle-in-cell method. Through the simulation results, it can be predicted that the background gas in the tube is one but not the most important factor resulting in pulse shortening, in order to broaden the pulse width of gas-filled RBWO, the pressure of the filled gas must be controlled in a proper value. The explosive emission in the surface of slow wave structure due to intense electric field is one of the most important factors causing pulse shortening in high power microwave tube.Some methods to overcome this kind of explosive emission are also given.     

Monte Carlo simulation driven time resolved photon fluence analysis

In this study, time resolved (TR) Monte Carlo (MC) simulation program code was run to generate photon fluencies with increasing time steps. TR MC simulation was performed for ten time series from 4 ps to 52 ps. Generated photon fluencies were transferred to the image analysis programming platform. Imaging device geometry was created for test purpose in image reconstruction programming platform environment. Forward model weight matrix functions were calculated during each time period for 38 sources, and 38 detectors according to the back-reflected imaging geometry. A homogenous phantom, which simulated tissue, was chosen. Depending on the homogeneous tissue optical properties, such as tissue absorption coefficient μa, and tissue scattering coefficient μs, photons emitted from the laser source positions; migrated differently inside the imaging tissue. Photons migrate inside the tissue by some multiplication factor of ps depending on the tissue type for each 100-micrometer vertical distance. Superficial photons come photodetector point fast, depend on the source-detector neighborhood distances and tissue optical properties, respectively. Time resolved diffuse optic tomography (TRDOT) imaging systems are an emerging biomedical optic imaging modality due to progressive electronic technologies are helping to build the systems faster and cheap. As such, emerging microelectronic technology is giving important access to design and implement compact laser sources and photodetector units. Vertical cavity surface emitting light (VCSEL) as laser source and single photon avalanche diode (SPAD) arrays as photodetector units are becoming in common use as important hardware tools for designers and researchers in this field. TR diffuse photon analysis should be done routinely for better understanding of TRDOT devices. Hence, MC simulation driven TR photon fluence analysis was done for such a purpose in this study.     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs.Different short channel field effects,such as fringing fields,junction-induced lateral fields and substrate fields,are carefully investigated,and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model.Through analytical model-based simulation,the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations.Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model.The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET.The short channel effects are found to be reduced in an SON,thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope.This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

Plasma and nanoparticle shielding during pulsed laser ablation in liquids cause ablation efficiency decrease

Understanding shielding cross-effects is a prerequisite for maximal power-specific nanosecond laser ablation in liquids(LAL).However,discrimination between cavitation bubble(CB),nanoparticle(NP),and shielding,e.g.,by the plasma or a transient vapor layer,is challenging.Therefore,CB imaging by shadowgraphy is performed to better understand the plasma and laser beam-NP interaction during LAL.By comparing the fluence-dependent CB volume for ablations performed with 1 ns pulses with reports from the literature,we find larger energy-specific CB volumes for 7 ns-ablation.The increased CB for laser ablation with higher ns pulse durations could be a first explanation of the efficiency decrease reported for these laser systems having higher pulse durations.Consequently,1 ns-LAL shows superior ablation efficiency.Moreover,a CB cascade occurs when the focal plane is shifted into the liquid.This effect is enhanced when NPs are present in the fluid.Even minute amounts of NPs trapped in a stationary layer decrease the laser energy significantly,even under liquid flow.However,this local concentration in the sticking film has so far not been considered.It presents an essential obstacle in high-yield LAL,shielding already the second laser pulse that arrives and presenting a source of satellite bubbles.Hence,measures to lower the NP concentration on the target must be investigated in the future.     

Experimental study on the single event latchup simulated by a pulse laser

This paper introduces major characteristics of the single event latchup (SEL) in CMOS devices. We accomplish SEL tests for CPU and SRAM devices through the simulation by a pulse laser. The laser simulation results give the energy threshold for samples to undergo SEL. SEL current pulses are measured for CMOS devices in the latchup state, the sensitive areas in the devices are acquired, the major traits, causing large scale circuits to undergo SEL, are summarized, and the test equivalence between a pulse laser and ions is also analyzed.     

基于MEDICI的CMOS反相器SEL特性分析

文章利用计算机模拟的方法分析了不同衬底CMOS反相器的单粒子闩锁（SEL）特性,分别对不同衬底CMOS反相器在电极分布和输出不同的情况下进行了研究,首先在不同电极分布时．通过电闩锁对器件进行模拟．得出不同电极分布时器件的维持电压,然后进行SEL模拟．根据模拟结果,我们发现在维持电压最小的电极分布情况下,粒子入射到阱-衬底结时,输出低电平时,器件产生闩锁后N衬底器件比P衬底器件闩锁电流大．输出高电平时．器件产生闩锁后P村底器件比N衬底器件的闩锁电流大。通过对不同衬底器件SEL阈值的测试,我们得到N村底器件比P衬底器件对SEL敏感．器件输出高电平时比输出低电平对SEL略敏感。     

DSP处理器单粒子翻转率测试系统的研制

航天器及其内部元器件在太空中会受到单粒子效应(SEE)带来的威胁,因此航天用电子器件在装备前必须进行抗SEE能力的测试评估。针对传统测试方法存在的测试系统程序容易在辐照过程崩溃、统计翻转数不准确、单粒子闩锁(SEL)辨别不清晰和忽略内核翻转统计等问题,设计了一种测试系统,通过片外加载与运行程序从而减少因辐照导致片内程序异常的现象;通过片外主控电路统计被测电路翻转数使统计翻转结果准确;通过主控电路控制被测电路时钟供给排除因频率增加导致电流过大而误判发生SEL的情况;通过内核指令集统计内核翻转数。实验结果表明,该测试系统可以实时全面地监测数字信号处理器(DSP)的SEE,并有效防止辐照实验器件(DUT)因SEL而失效。     

Fault-tolerant TMR and DMR circuits with latchup protection switches

The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.     

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n⁺-p⁺ spacing L longer than 8 μm, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 μm     

输出对CMOS反相器SEL特性的影响评估

文中通过计算机模拟的方法分析了器件在不同输出电平时,CMOS反相器单粒子闩锁（SEL）特性的变化。通过对器件输出电平不同时,不同衬底的CMOS反相器进行仿真研究,我们得出,P衬底器件输出为高电平时比输出为低电平时得到的闩锁电流大,而N衬底器件在输出不同时,得到的闩锁电流大小相近。对于同种衬底的器件在输出不同时对SEL的敏感性几乎相同。在深亚微米的器件中,输出对器件SEL特性的影响均较大,需要在研究器件SEL特性时把其考虑在内。     

深亚微米CMOS反相器的单粒子瞬态效应研究

针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值范围。同时,开展脉冲激光模拟单粒子瞬态效应试验,定位该器件单粒子瞬态效应的敏感区域,捕捉不同辐照能量下器件产生的单粒子瞬态脉冲,确定单粒子瞬态效应的阈值范围,并与仿真结果进行对比分析。     

Latchup suppression in fine-dimension shallow p-well CMOS circuits

The high packing density required for VLSI CMOS circuits leads to enhanced performance of the inherent parasitic bipolar devices, and thus latchup becomes a major problem. One of the most attractive techniques for overcoming this is to fabricate the devices on n-on-n⁺epitaxial substrate material. This paper deals with latchup suppression by such a technique in fine-dimension CMOS circuits based on very shallow p-wells. Experimental results demonstrate that latchup may be eliminated in structures with p-well depths as shallow as 0.8 µm at supply voltages up to 10 V and temperatures up to 140°C. Furthermore, this may be achieved with no significant degradation of other aspects of device or circuit performance. A simple lumped model equivalent circuit has been used to predict latchup characteristics where appropriate, and in general this gives good agreement with experiment.     

Static and transient latchup simulation of VLSI-CMOS with an improved physical design model

We are presenting an improved latchup design model for static and transient latchup simulation of VLSI CMOS devices. The model is based on a decomposition of the CMOS structure into a network of analytically described current elements for both majority and minority carriers. Average doping densities and geometrical parameters are the physically based input data. For the modeling of the 2-D majority-carrier flow, transmission-line elements are introduced, especially in the inhomogeneously doped transition region between the substrate and an epitaxial layer. For modeling the transient current behavior, diffusion and space-charge capacitances are used. The model yields very good agreement with measurements both for static and transient triggering modes. Due to the physically reasonable assumptions used in the model equations, the influence of design variations on latchup characteristics can be predicted adequately without new parameter fitting.