短沟道双栅MOSFET二维表面势解析模型

采用分解电势的方法求解二维泊松方程,建立了考虑电子准费米势的短沟道双栅MOSFET的二维表面势模型,并在其基础上导出了阈值电压、短沟道致阈值电压下降效应和漏极感应势垒降低效应的解析模型。研究了不同沟道长度、栅压和漏压情况下的沟道表面势,分析了沟道长度和硅膜厚度对短沟道效应的影响。研究结果表明,电子准费米势对开启后的器件漏端附近表面势有显著影响,新模型可弥补现有模型中漏端附近表面势误差较大的缺点;对于短沟道双栅MOSFET,适当减小硅膜厚度可抑制短沟道效应。     

Analytical Drain Current Modeling and Simulation of Triple Material Gate-All-Around Heterojunction TFETs Considering Depletion Regions

Semiconductors - This paper deals with electrostatic behavior of triple-material gate-all-around hetero-junction tunneling field-effect transistors (TMGAA-HJTFET) device. The model is advantageous...     

TF SOI PMOSFET的导电机理及漏电流的二维解析模型

从薄膜积累型 (TF AM) SOIPMOSFET的栅下硅膜物理状态随外加正栅压和漏压的变化出发 ,对其在 -5 .0 V背栅偏压下的导电机理进行了比较深入的理论分析 ,推导出了各种正栅压和漏压偏置条件下漏电流的二维解析模型 ,为高温 TF AM SOIPMOSFET和 CMOS数字电路的实验研究奠定了一定的理论基础 ,也为设计高温 SOI PMOSFET和 CMOS数字电路提供了一定的理论依据。     

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-μm operational transconductance amplifiers having equal 50-μA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz^1/2, and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes. David M. Binkley (S’81, M’82, SM’93) joined the University of North Carolina at Charlotte in 2000 as an associate professor in the electrical and computer engineering department. Dr. Binkley and his students are researching analog design and testing methodologies including micropower, low-noise analog CMOS design for neural implants and radiation hardened, deep space applications. Dr. Binkley was a cofounder and vice president of integrated circuit development at Concorde Microsystems and senior scientist at CTI PET Systems where he designed both discrete and integrated CMOS electronics for positron emission tomography (PET) medical imaging systems. Concorde and CTI are currently part of Siemens Medical Solutions. Dr. Binkley received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Tennessee, Knoxville. He is the author of over 60 papers in analog circuit design and instrumentation and holds five U.S. patents. Dr. Binkley is currently writing the book, Analog CMOS Design, Tradeoffs and Optimization, for John Wiley and Sons with planned publication in 2006. Benjamin J. Blalock (S’, M’) received his B.S. degree in electrical engineering from the University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He joined the Department of Electrical and Computer Engineering at Mississippi State University in 1996 and the University of Tennessee in 2001. His current research focus includes mixed-signal/mixed-voltage circuit design for systems-on-a-chip in SOI technology, analog IC design for extreme environments, multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, and bio-microelectronics. He has over 25 publications in the field of analog IC design and has contributed to The Circuits and Filters Handbook. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems, Inc. James M. Rochelle (M’84) received the B.S., M.S., and Ph.D. degrees in Electrical engineering from the University of Tennessee, Knoxville. From 1965 to 1982 he was with the Instrumentation and Controls Division of the Oak Ridge National Laboratory. From 1982 to 2001, he was Associate Professor of Electrical and Computer Engineering at the University of Tennessee, Knoxville teaching and conducting research in integrated circuit device modeling and mixed-signal integrated circuit design. In 2001 he retired from academia and is presently an emeritus associate professor and vice president of ASIC development at Concorde Microsystems, Inc., now part of Siemens Medical Solutions located in Knoxville, Tennessee. His current research interests are mixed-signal ASIC's for medical imaging readout electronics and micropower battery-powered devices.     

Impact of Scaling on Analog Performance and Associated Modeling Needs

This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below 90 nm are simulated at the device level to show trends in analog performance metrics and to evaluate the impact of nonminimum gate length and alternate doping profiles. Results indicate that the modeling of moderate-to-weak inversion behavior will continue to grow in importance. Simulations suggest that using nonminimum length and drain-side engineered devices at the 45-nm technology node offers an attractive degree of freedom for analog circuit design.     

考虑量子效应的超薄体双栅肖特基源漏MOSFET电流解析模型

推导了超薄体双栅肖特基势垒MOSFET器件的漏电流模型,模型中考虑了势垒高度变化和载流子束缚效应.利用三角势垒近似求解薛定谔方程,得到的载流子密度和空间电荷密度一起用来得到量子束缚效应.由于量子束缚效应的存在,第一个子带高于导带底,这等效于禁带变宽.因此源漏端的势垒高度提高,载流子密度降低,漏电流降低.以前的模型仅考虑由于镜像力导致的肖特基势垒降低,因而不能准确表示漏电流.包含量子束缚效应的漏电流模型克服了这些缺陷.结果表明,较小的非负肖特基势垒,甚至零势垒高度,也存在隧穿电流.二维器件模拟器Silvaco得到的结果和模型结果吻合得很好.     

考虑量子效应的超薄体双栅肖特基源漏MOSFET电流解析模型

推导了超薄体双栅肖特基势垒MOSFET器件的漏电流模型,模型中考虑了势垒高度变化和载流子束缚效应.利用三角势垒近似求解薛定谔方程,得到的载流子密度和空间电荷密度一起用来得到量子束缚效应.由于量子束缚效应的存在,第一个子带高于导带底,这等效于禁带变宽.因此源漏端的势垒高度提高,载流子密度降低,漏电流降低.以前的模型仅考虑由于镜像力导致的肖特基势垒降低,因而不能准确表示漏电流.包含量子束缚效应的漏电流模型克服了这些缺陷.结果表明,较小的非负肖特基势垒,甚至零势垒高度,也存在隧穿电流.二维器件模拟器Silvaco得到的结果和模型结果吻合得很好.     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.     

一个连续且解析的SOI LDMOS表面势模型

提出了一个实现全耗尽与部分耗尽自动转换的体接触SOI LDMOS连续解析表面势模型.采用PSP的精确表面势算法求解SOI器件的表面势方程,得到了解析的以栅压和漏压为变量的SOI器件正、背硅/氧化层界面的表面势.修正了全耗尽状态下的反型层电荷和体电荷表达式,结合PSP的模型方程,给出连续解析的体接触SOI LDMOS直流模型.仿真结果与实验数据比较,二者吻合得很好,表明该模型能精确表征SOI LDMOS直流特性.     

一个连续且解析的SOI LDMOS表面势模型

提出了一个实现全耗尽与部分耗尽自动转换的体接触SOI LDMOS连续解析表面势模型.采用PSP的精确表面势算法求解SOI器件的表面势方程,得到了解析的以栅压和漏压为变量的SOI器件正、背硅/氧化层界面的表面势.修正了全耗尽状态下的反型层电荷和体电荷表达式,结合PSP的模型方程,给出连续解析的体接触SOI LDMOS直流模型.仿真结果与实验数据比较,二者吻合得很好,表明该模型能精确表征SOI LDMOS直流特性.     

高频地波雷达系统优化控制的研究与建模

现代电子工业技术的发展使高频地波雷达的功能不断扩增,导致雷达系统控制十分复杂。因此,需要通过系统的性能评估、优化及智能控制使之能够在各种情况下发挥其最大效能。依据高频地波雷达的特点和探测目标类型进行系统建模仿真。考虑不同模糊控制方法在高频地波雷达系统中的可行性,将遗传算法和粒子群优化算法等方法与模糊控制结合实现对雷达系统的优化控制。通过对雷达信号频率、功率和相参积累时间的模糊控制达到期望的工作性能。利用 Matlab设计 GUI控制界面。     

Evaluation of Packaging-Induced Performance Change for Small-Scale Analog IC

The impact of packaging-induced circuit performance changes for a small-scale integrated circuit (IC) smaller than 1.0 mm $^{2}$ has been evaluated by a new method with specially designed test chips. Analog circuits such as power management ICs for portable electronic devices are small-scale chips and require high-accuracy operation. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence, after which one distribution chart was reproduced from all of the measurement results. The present method enables the characteristic distribution on the chip surface to visualize not only the electrical parametric distribution but also the residual stress distribution, even though small-scale ICs have a limited number of bonding pads. In addition, a new method for evaluating the circuit performance change of an analog circuit due to stress-induced parametric changes is presented.      

Demonstration of a Self-Synchronized Polyphase Sampling and Demultiplexing Scheme for Radio-Frequency Analog Signals

A novel self-synchronizing optoelectronics polyphase scheme for sampling and demultiplexing radio-frequency (RF) signals is demonstrated. One unique feature of this approach is that the optically sampled RF signal always remains in the electrical domain and thus eliminates the need for electrical-to-optical and back to electrical conversions. Furthermore, the simplicity and ease of construction of the scheme readily allows it to be scaled to obtain high sampling rates. As a proof of concept, a 100-MHz RF electrical signal sampled at the rate of 1.28 GS/s and then demultiplexed into four 320-MHz signals was experimentally demonstrated.     

Analytical modeling and simulation of germanium single gate silicon on insulator TFET

This paper proposes a new two dimensional（2D） analytical model for a germanium（Ge） single gate silicon-on-insulator tunnel field effect transistor（SG SOI TFET）. The parabolic approximation technique is used to solve the 2D Poisson equation with suitable boundary conditions and analytical expressions are derived for the surfacepotential,theelectricfieldalongthechannelandtheverticalelectricfield.Thedeviceoutputtunnellingcurrent is derived further by using the electric fields. The results show that Ge based TFETs have significant improvements inon-currentcharacteristics.Theeffectivenessoftheproposedmodelhasbeenverifiedbycomparingtheanalytical model results with the technology computer aided design（TCAD） simulation results and also comparing them with results from a silicon based TFET.     

高性能模拟前端AD7714及其应用

AD7714是一个完整的用于低频测量应用的模拟前端。其主要特点是:使用Σ-Δ转换技术,转换精度高;具有片内可编程增益放大器和低通数字滤波器;具有SPI通信接口等。通过实验,提炼出了AD7714技术说明书中没有明确的特性和技术指标,纠正了其中的错误,讨论了在应用上的技术要点、缺点,介绍了在“863”重点引导项目和安徽省“十五”重点攻关项目中的应用。     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

Refinement of an Analytical Approximation of the Surface Potential in MOSFETs

通过在表面势公式中增加一高阶近似项,大大提高了传统表面势的解析近似精度.改进前通用参数的精度一般达到1nV量级,某些情况下只能达到0.03mV.改进后的方法在所有情况下精度都达到1pV量级.同时,改进后的近似方法消除了原有方法误差曲线中的毛刺现象.     

MOSFET表面势解析近似方法的改进

通过在表面势公式中增加一高阶近似项,大大提高了传统表面势的解析近似精度.改进前通用参数的精度一般达到1nV量级,某些情况下只能达到0.03mV.改进后的方法在所有情况下精度都达到1pV量级.同时,改进后的近似方法消除了原有方法误差曲线中的毛刺现象.