Margins of a 16-ps/bit interferometer shift register

Static and dynamic properties of an interferometer with five equal Josephson junctions are investigated as a single-flux quanta shift-register model. A flux quantum is stored in any loop without a bias current or magnetic field. A flux quantum is shifted from one interferometer loop to the adjacent one by applying a magnetic-field control pulse only to one in terferometer loop at a time. Shift current margins determined statically and dynamically are larger than about ±30 percent; the write current margins are ±25 percent. Within these tolerances, and for a maximum Josephson current density of 10 kA/ cm², delays of 16 ps/bit, including shift and write, have been simulated.     

HTS SFQ logic circuit built with YBCO grain boundary junctions

We have designed, fabricated, and operated an SFQ RS flip–flop based on YBCO grain boundary junctions formed on a SrTiO₃ bi-crystal substrate. The circuit consisted of a read SQUID and an RS flip–flop, which were magnetically coupled together. The circuit operated correctly in the temperature range of 65–71 K. Especially, at 71 K, this circuit operated correctly over the 100 reset–set operations without making errors. We also measured the effect of noise on switching a Josephson junction to the voltage state in an SFQ circuit.     

The flux shuttle—A Josephson junction shift register employing single flux quanta

A shift register is described which employs as information bits the flux quantum vortices occurring in Josephson junctions of extended dimensions. The positions of the vortices can be controlled and manipulated by an appropriately designed circuit geometry and by application of currents and magnetic fields. The time required for switching of the position of a vortex can approach the period of the Josephson plasma oscillation (∼10 ps) and the intrinsic energy dissipation is typically ≲ 10^-18J/shift.     

Logic gates with shaped Josephson junctions

Long (L//spl lambda//SUB j/>5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (/spl lambda//SUB j/ being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed sidelobes, providing good logic gain and permitting logic fan-in with multiple control lines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I/SUB G//spl sime/6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3/spl times/10/SUP -15/ J.     

Josephson shift registers

A review of Josephson shift-register circuits that have been designed, fabricated, or tested is presented with emphasis on work in the 1980s. Operating speed is most important, since it often limits system performance. Older designs used square-wave clocks, but most modern designs use offset sine waves, with either two or three phases. Operating margins and gate bias uniformity are key concerns. The fastest measured Josephson shift register operated at 2.3 GHz, which compares well with a GaAs shift register that consumes 250 times more power. The difficulties of high-speed testing have prevented many Josephson shift registers from being operated at their highest speeds. Computer simulations suggest that 30-GHz operation is possible with current Nb/Al ₂O₃/Nb technology. Junctions with critical current densities near 10 kA/cm² would make 100-GHz shift registers feasible     

Modeling of HTS Josephson junctions

We discuss recent developments for HTS Josephson junctions: (i) isolated (S/I) and resonantly coupled (S/I/S) Andreev interface states, (ii) d-wave models with resonantly coupled midgap states for ab-plane junctions and (iii) resonant tunneling models for c-axis junctions.     

A surface-charge shift register with digital refresh

A digital shift register using the surface-charge transistor structure in which adjacent rows propagate in opposite directions and which has refresh turn-around circuits at the ends of each row is described. Two process compatible refresh circuits requiring only four times the basic bit storage area have been designed, and a test circuit composed of two 16-bit shift registers that propagate in opposite directions and are connected by these circuits has been built and tested. The regeneration characteristics of these refresh circuits have been measured as a function of transfer time in both the complete and partial transfer modes (`fat zero'). Operation of one of these 32-stage shift registers and its refresh at 10 MHz is presented.     

Picosecond applications of Josephson junctions

The behavior of simple superconducting circuits in the picosecond regime is described in a comprehensive way, with primary emphasis being given to the step function and pulse responses of these circuits. Topics receiving detailed discussion include Josephson-junction modeling with both the microscopic and shunted-junction models. Limitations of the shunted-junction model are explored by comparing it with experimental results and with the microscopic model. An approximate evaluation is given of the important dynamical properties of junctions made with the dominant fabrication technology (Pb-alloy systems), as a function of tunneling barrier thickness. Rounding out the device aspects of the discussion, we describe in detail the properties of superconducting microstrip transmission lines, with an emphasis on their high-speed behavior. Turning to simple circuits we review experimental results on the measurement of picosecond regime transient signals. The concept of turn-on delay is analyzed anew, providing simplified and extended results. Details of concepts for pulse height and pulsewidth measurements are explored, leading to the conclusion that the time resolution of superconducting circuits is limited to approximately the period of one plasma oscillation. With present Pb-alloy fabrication technology this limit is 2 ps.     

Analog capacitance ROM with IGFET bucket-brigade shift register

A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.     

互控?钟控移位寄存器序列

提出了一种新的互控钟控移位寄存器模型.该模型具有设备简单,易于实现,并且产生的序列周期长,线性复杂度高,抗攻击能力强等特点.这种模型被进一步改进,利用它可以生成更好的序列.     

A new static shift register with dynamic transfer

A new shift register of extremely low d.c. standby power has been implemented in a simplified bipolar transistor technology using 4 mask steps up to metallization and 2 diffusions only. The bit density is 250 bit/mm² with 5 μm line dimensions, the standby power 0·1 μW/bit and the cycle time 150 nsec at 150 μW/bit. The shift register features a new operation principle: In standby, it is truly static, whereas for shifting the memory operates dynamically utilizing the effect that a dynamically unbalanced flip-flop switches into a definite state. The dynamic charge unsymmetry originates from the state of the previous cell and is shifted to the next one after each clock cycle.     

Silicon-coupled Josephson junctions and super-Schottky diodes with coplanar electrodes

Superconducting devices with coplanar electrodes have been fabricated using electron-beam lithography to define the smallest feature. The devices each consist of two Pb-In alloy electrodes, 20 µm wide, deposited on a clean, degenerately doped silicon substrate. The two electrodes are separated by a thin (100-300-nm) gap. Electron-beam lithography is used to define the gap, and sputter etching to remove the underlying alloy film. Depending on the width of the gap and the condition of the metal-semiconductor interface, these devices displayed either Josephson or super-Schottky diode behavior. The Josephson devices show a high degree of robustness and hadI_{c}Rproducts in the range 200-800 µV at 4.2 K. The super-Schottky diodes had current sensitivities S in the range 1000-1300 V^-1when measured at 4.2 K.     

A low-latency asynchronous shift register

In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.     

Superconducting memory device using Josephson junctions

A superconducting storage device is proposed in which a Josephson tunnelling junction, switched by a control film strip, replaces the cryotron in a one-cryotron-per-bit storage cell. The device should be fast, work at 4.2° K and require a simple technology, which must, however, yield reproducible thin Josephson tunnelling layers.     

General energy relations for Josephson junctions

The Josephson junction acts as a nonlinear lossless inductor and can be applied for mixing and parametric amplification in the microwave region. Since an alternating current can be generated in the junction by an applied dc voltage, a dc power flow must be taken into consideration. Energy relations for the Josephson junction are derived which are similar to the Manley-Rowe equations but with an additional term for the dc power. These equations show the possibility of realizing dc-pumped parametric amplifiers.     

A bipolar four-phase dynamic shift register

A 512-b dynamic shift register is integrated on 6.4-mm/SUP 2/ active chip area. The frequency range is from 100 Hz to 3 MHz. At 1 MHz the power dissipation is 20 mW. The performance of the shift register is insensitive to spread in process parameters because the information is regenerated in each cell. The comparison of the measured and the calculated working range shows the essential influence of all parasitic capacitances.     

Low power serial-parallel dynamic shift register

Serial-to-parallel shift registers have a wide range of applications. These registers are commonly found in communication systems and interfaces between electronic peripherals. Presented is a unique low power area efficient 128-bit serial-to-parallel shift register design that contains only four transistors per stage. The new register uses the capacitive bootstrapping technique to overcome the threshold voltage drop of MOSFETs. This logic family is named non-ratioed bootstrap logic (NRBL). Target applications are dense smart sensor arrays and image sensors.     

Rijndael移位寄存器实现方案

(1)引 言分组加密算法Rijndael在2000年10月2日被确定为美国高级加密标准AES(Advanced Encryption Standard)。在经过严格的安全分析后,从2002年5月26日起作为官方标准(FIPS197)正式实施,取代DES在未来30年里保护美国联邦政府非机密敏感信息,同时在商业、金融和IT等领域获得广泛应用。Rijndael算法是一个分组长度为128比特、密钥可取128、192和256三种长度的分组密码。16字节的分组被组织成称为状态的4×4字节矩阵,其中的列可看成一个4字节的字。密码变换就在这样的字节、行和列上实施,以圈变换为单位连续迭代若干次(对应不同密钥长…     

The bipolar transistor bucket-brigade shift register

An analysis of the bipolar transistor bucket-brigade shift-register operation is presented for comparison to other charge-transfer shift-register schemes. It is shown that incomplete charge transfer, the most important performance limiting effect for the charge-coupled device and the IGFET bucket brigade, is very small under most practical operating conditions for the bipolar transistor bucket brigade. In addition to charge loss due to finite transistor current gain h/SUB fe/ the next most important performance limitation comes from collector-emitter capacitance. It is shown that this collector-emitter capacitance leads to reduced analog time delay on transfer through the register and to signal attenuation effects similar to those resulting from incomplete charge transfer. Using the results of the analysis, experimental data reported by Sangster are discussed and a comparison of the advantages and disadvantages of the bipolar bucket-brigade register with the MOS charge-transfer registers is made.