Impurity diffusion behavior of bipolar transistor underlow-temperature furnace annealing and high-temperature RTA and itsoptimization for 0.5-μm Bi-CMOS process

A low-temperature-processed (800-850°C) bipolar transistor design suitable for the high-performance 0.5-μm BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region. and insufficient arsenic diffusion from the poly Si are serious considerations if low-temperature furnace annealing is used. If high-temperature rapid thermal annealing (RTA) is used instead of low-temperature furnace annealing, these problems are resolved. Through impurity diffusion behavior and related electrical bipolar transistor design in the high-performance 0. 5-μm Bi-CMOS process are proposed. The As-P emitter and selectively implanted collector structures, annealed using RTA, were found to be suitable for the advanced Bi-CMOS process     

Improvement of P-channel SOI LDMOS transistor by adapting a newtapered oxide technique

On-resistance of P-channel REduced SURface Field (RESURF) lateral double-diffused MOS (LDMOS) transistors has been improved by using a new tapered TEOS field oxide on the drift region of the devices. The new tapered oxidation technique provides better uniformity, less than 3%, and reproducibility. With the similar breakdown voltage (V_B), at V_gs=-5.0 V, the specific on-resistance (R_sp) of the LDMOS with the tapered field oxide is about 31.5 mΩ·cm ², while that of the LDMOS with the conventional field oxide is about R_sp=57 mΩ·cm². The uniformities of R_sp and V_B are less than 5 and 3%, respectively     

Improvement of InP MISFET characteristics using infra-red lamp annealing

An infra-red lamp-annealing technique was employed for postannealing Si ion-implanted InP substrates. The effective electron mobility (?eff) of SiO2-InP metal-insulator-semiconductor field-effect transistors fabricated using infrared lamp annealing is remarkably temperature-dependent. The maximum ?eff is ? 11000 cm2/Vs at 75 K and 1500?2500 cm2/Vs at room temperature.     

Flat band voltage shift and oxide properties after rapid thermal annealing

The flat band voltage (V_fb) shift observed for MOS samples exposed to rapid thermal annealing (RTA) (N₂, 20 s, 1040°C) is examined for (1 0 0), (1 1 0) and (1 1 1) orientation-silicon substrates. Using a mercury gate C–V system, the V_fb shift can be attributed to changes in the electronic properties of the oxide layer and not polysilicon gate effects, as had previously been suggested. In addition, this work indicates that the flat band voltage shift results from a reduction of interface and fixed oxide charge due to the RTA process. The interface and oxide charge densities are related to the density of available bonds for each surface orientation, both before and after an RTA step. Based on these results, we argue that the V_fb shift following RTA is primarily due to a reduction of fixed positive charge in the oxide, and to a lesser degree, to a reduction of negative interface charge. The net effect is that the RTA step reduces the total oxide charge density.     

Effects of combined NO and forming gas annealing on interfacial properties and oxide reliability of 4H-SiC MOS structures

The effects of NO and forming gas post oxidation annealing treatments on the interfacial properties and reliability of thermal oxides grown on n-type 4H-SiC (0001) Si face have been investigated in this study. The results show that forming gas annealing (FGA) treatment has limited effect on interface trap density (D_it) while it results in an improvement of the insulating properties of thermal oxide with uniform high FN barrier height (2.56 eV), high field-to-breakdown (10.71 MV/cm) and charge-to-breakdown (0.078 C/cm²). On the other hand, NO annealing causes a drastic reduction in D_it in the entire energy level, but in the case of reliability, it is not so effective as FGA, with lower barrier height (2.52 eV), field-to-breakdown (10.08 MV/cm), charge-to-breakdown (0.025 C/cm²) and worse uniformity of oxide. The combined NO&FGA treatment was also studied. It leads to a significant reduction in interface trap density further, especially in deep energy level (E_C-E_T ≥ 0.4 eV). As for reliability, it brings about uniform barrier height (2.69 eV), field-to-breakdown (10.15 MV/cm) and charge-to-breakdown (0.024 C/cm²). Taking interfacial properties and reliability into account, combined NO&FGA treatment is a promising POA technique for fabrication of high-quality SiC MOS devices.     

MOSFET characteristics with poly-Si/HfAlON gate stacks using ultra-thin UV-ozone interfacial oxide

This paper conducts a comprehensive evaluation of the electrical characteristics of the poly-silicon gated n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) with hafnium-aluminum-oxynitride (HfAlON) gate dielectric with interfacial ultraviolet-ozone (UV-O₃) oxide or chemical oxide. Interfacial UV-O₃ oxide exhibits well-controlled interfacial properties due to self-saturated growth and thick-oxide-comparable density, which is beneficial to suppress interfacial re-oxidation and reduces surface roughness. Compared with interfacial chemical oxide, the interfacial UV-O₃ oxide obviously improves both gate insulating and interface characteristics, including breakdown voltage increments, reduced gate leakage current, and as-deposited traps. In addition, the HfAlON gate stack with UV-O₃ interface oxide also shows encouraging nMOSFET device performances, with a small subthreshold swing, high electron mobility, saturation drain current, and negligible stress-induced trap generation. The results clearly suggest that the high-density interfacial UV-O₃ oxide possess a high potential to be integrated with further high-k dielectric applications.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

Improvement of thin-gate oxide integrity using through-silicon-gate nitrogen ion implantation

A simple and manufacturable technique to improve thin-gate oxide integrity using nitrogen implant through a polycrystalline-silicon (poly-Si) gate MOS structure is described. The Auger depth profile of the film, after 1100°C oxidation cycle, shows nitrogen pile-up at both poly-Si and substrate interfaces, similar to the NH3annealed thermal oxide. Interface-state generation and charge to breakdown under high-field/current stress are significantly improved. Fowler-Nordheim tunneling characteristics and measured capacitance reveal a 3-percent increase in the film thickness. Negative bulk charge trapping is similar to that of thermal oxide film. These properties can be attributed to the formation of the nitrogen-rich layers at both film interfaces, rather than the bulk of the film.     

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.     

Enhanced storage/operation stability of small molecule organic photovoltaics using graphene oxide interfacial layer

Graphene and graphene oxide (GO) have been applied in flexible organic electronic devices with enhanced efficiency of polymeric photovoltaic (OPV) devices. In this work, we demonstrate that storage/operation stability of OPV can be substantially enhanced by spin-coating a GO buffer layer on ITO without any further treatment. With a 2 nm GO buffer layer, the power conversion efficiency (PCE) of a standard copper phthalocyanine (CuPc)/fullerene (C₆₀) based OPV device shows about 30% enhancement from 1.5% to 1.9%. More importantly, while the PCE of the standard device drop to 1/1000 of its original value after 60-days of operation-storage cycles; those of GO-buffered device maintained 84% of initial PCE even after 132-days. Atomic force microscopy studies show that CuPc forms larger crystallites on the GO-buffered ITO substrate leading to better optical absorption and thus photon utilization. Stability enhancement is attributed to the diffusion barrier of the GO layer which slow down diffusion of oxygen species from ITO to the active layers.     

Improvement of mechanical and electrical stabilities of flexible organic thin film transistor by using adhesive organic interlayer

A newly synthesized organic material, oligo(3-methylsulfanylthiophene), was applied as an adhesive interlayer between the gold source/drain electrodes and the pentacene semiconductor layer in flexible, bottom-gated, organic thin film transistors (OTFTs). The cyclic bending tests showed that the electrical properties of the devices with the thermally evaporated interlayer were more stable than those of the device with no interlayer. The interlayer also reduced the contact resistance between Au and the pentacene layer. These results indicate that the interlayer is very useful in enhancing the mechanical and electrical stabilities of the OTFTs under repetitive mechanical bending as well as the electrical performance.     

PEO作阴极修饰层提高有机光伏电池的稳定性

采用聚氧化乙烯(PEO)作为聚合物太阳能电池的阴极修饰层,以P3HT:PCBM为活性层制备了聚合物本体异质结太阳能电池。考察了PEO的厚度对器件光伏性能及稳定性的影响。比较了加入PEO修饰层前后器件的稳定性,研究了采用PEO修饰层前后器件电阻的差异。结果表明:加入PEO作为阴极修饰层后器件的光电性能(JSC,VOC,FF,PCE)均有明显提高,而器件的串联电阻Rs则有了明显降低。没有阴极修饰层的器件的初始光电转换效率为1.92%,90 h后衰减为初始值的5%;而加入PEO修饰层后初始光电转换效率为3.36%,90 h后仅衰减为初始值的20%,光电转换效率提高了75%,稳定性提高了3倍。     

Improvement of FinFET electrical characteristics by hydrogen annealing

Hydrogen anneal is used during FinFET processing to round off the corners of the silicon fins prior to gate oxidation and to smooth the surface of the fin sidewalls. This procedure greatly improves gate leakage and, in addition, reduces the width of the fins, resulting in a lower threshold voltage and improved drain-induced barrier lowering (DIBL) characteristics. Reduction of the leakage current by up to four orders of magnitude is obtained after edge rounding by hydrogen annealing. In addition, a 50% decrease of DIBL is observed, due to fin width reduction.     

Effects of solid-state annealing on the interfacial intermetallics between tin-lead solders and copper

The interfacial intermetallics between Cu and solder were studied for four Sn-Pb compositions at the annealing temperatures of 125°C, 150°C, and 175°C for up to 30 days. The η-phase (Cu₆Sn₅) layer formed during reflow continues to grow during annealing. An additional layer of ɛ-phase (Cu₃Sn) forms at the η/Cu interface after an incubation annealing time. The thickness results fit a power-law relationship against time with average exponents 0.69 and 0.44 for the η phase and the ɛ phase, respectively. On prolonged annealing, the proportions of the individual phases in the total layer reach a steady state.     

Ultradry annealing after polysilicon electrode formation forimproving the TDDB lifetime of ultrathin silicon oxide films in MOSdiodes

Effects of ultradry annealing on time-dependent dielectric breakdown (TDDB) lifetime (T_TDDB) were investigated for Si MOS diodes with 5-nm-thick silicon oxide and P-doped polysilicon gate electrode films. This annealing was performed at 800°C in ultradry N₂ of less than 1-ppm moisture concentration after the electrode formation. Under an accumulation-bias stress condition, T_TDDB for the ultradry-annealed n-type Si diodes was larger than that for the conventionally annealed ones, while such T _TDDB enhancement was not confirmed in the p-type ones. Since positive charges induced near anode-side oxide interfaces are closely related to T_TDDB, the T_TDDB enhancement for the ultradry-annealed n-type Si diodes probably reflects a qualitative improvement of the anode-side, i.e., gate-electrode-oxide, interfaces by ultradry annealing     

Effects of RTA temperatures on conductivity and micro-structures of boron-doped silicon nanocrystals in Si-rich oxide thin films

In this work, the B-doped Si rich oxide (SRO) thin films were deposited and then annealed using rapid thermal annealing (RTA) to form SiO₂-matrix silicon nanocrystals (Si NCs). The effects of the RTA temperatures on the structural properties, conduction mechanisms and electrical properties of B-doped SRO thin films (BSF) were investigated systematically using Hall measurements, Fourier transform infrared spectroscopy and Raman spectroscopy. Results showed that the crystalline fraction of annealed BSF increased from 41.3% to 62.8%, the conductivity was increased from 4.48×10⁻³ S/cm to 0.16 s/cm, the carrier concentration was increased from 8.74×10¹⁷ cm⁻³ to 4.9×10¹⁸ cm⁻³ and the carrier mobility was increased from 0.032 cm² V⁻¹ s⁻¹ to 0.2 cm² V⁻¹ s⁻¹ when the RTA temperatures increased from 1050 °C to 1150 °C. In addition, the fluctuation induced tunneling (FIT) theory was applicable to the conduction mechanisms of SiO₂-matrix boron-doped Si-NC thin films.     

Effect of interfacial oxide on Ge MOSCAP and N-MOSFET characteristics

The effect of electrical quality of interfacial oxide on Ge MOSCAP and MOSFET characteristics is investigated. Different growth conditions are studied to optimize the interfacial layer. CV and D_it measurements are done for accurate comparison of different gate dielectric stacks. Optimized ozone oxidation process is integrated with Co-induced dopant activation to fabricate Ge N-MOSFETs. Forty percent improvement in inversion electron mobility is demonstrated with optimized GeO₂ passivation. The highest electron mobility is reported in bulk Ge N-MOSFETs with GeO₂/Al₂O₃ gate dielectric stack.     

KH550-GO复合栅介质低压氧化物薄膜晶体管

采用旋涂法制备硅烷偶联剂-氧化石墨烯(KH550-GO)新型复合栅介质薄膜,由于栅介质层和沟道层界面处明显的双电层效应,单位面积电容高达2.18×10~(–6)F/cm~2。通过自组装法,借助磁控溅射仪,仅需一次掩膜,即可同时生成晶体管的沟道与源漏电极。利用半导体参数分析仪在室温黑暗的条件下测量该晶体管的电学特性,结果表明,KH550-GO栅介质氧化物薄膜晶体管具有优良的电学性能,其工作电压仅为2 V、饱和电流为580μA、亚阈值摆幅108 m V/dec、开关比4×10~7、场效应迁移率16.7 cm~2·V~(-1)·s~(-1)。     

Effects of nitric oxide annealing of thermally grown silicondioxide characteristics

The effects of nitric oxide (NO) annealing on conventional thermal oxides are reported in this letter. The oxide thickness increase, resulting from NO annealing, is found to be only a few angstroms (<0.5 nm) and independent on the initial oxide thickness. Furthermore, both the electrical and physical characteristics are improved. This technique is expected to achieve sub-5 nm high quality ultrathin dielectric films for the applications in EEPROM's and ULSI