110GHz阻性平衡三倍频器设计

本文介绍了一种基于阻性肖特基二极管芯片UMS DBES105a的110GHz三倍频器,通过两个芯片反向并联形成了平衡结构,同时提高了倍频器的功率承受能力。电路设计中使用二极管三维电磁模型,匹配设计时未设计专门的输入过渡和滤波器,而是直接经行匹配设计,提供了更多的可优化参量,以达到最佳的匹配效果和带宽。经过HFSS和ADS联合仿真,在频率为31~44GHz,功率为20d Bm的驱动信号激励下,三倍频器输出频率大于7d Bm,最大输出功率为9.1d Bm@105GHz。     

基于石英基片的二毫米频段三倍频器的研制

介绍了一个基于石英基片的二毫米频段三倍频器.采用反向并联变容二极管对结构实现倍频.建立了该二极管管对的等效电路模型并提取了模型参数.设计实现的倍频器输入为K型接头结构,输出为WR-8波导结构.获得的倍频器在输出频率为112.8～118.2 GHz范围内,输出功率大于0 dBm,最大输出功率超过2 dBm,最小倍频损耗为...     

260 GHz GaN高功率三倍频器设计

基于GaN太赫兹二极管芯片,采用非平衡式电路结构,设计了一款260 GHz三倍频器。采用GaN肖特基二极管芯片提高电路的耐受功率和输出功率;采用“减高+减宽”的输出波导结构抑制二次谐波;采用高低阻抗带线结构设计了倍频器的输入滤波器和输出滤波器。测试结果显示,该三倍频器在261 GHz峰值频率下,实现最大输出功率为69.1 mW,转换效率为3.3%,同时具有较好的谐波抑制特性。     

W波段三倍频器的设计与仿真

分析了平衡倍频器的工作原理和结构,并使用商用肖特基势垒二极管DBES105a设计一个W波段宽带三倍频器。电路采用微带线制作,并安装在波导中。倍频器电路的波导微带过渡结构、低通滤波器和匹配枝节均使用电磁场分析软件HFSS仿真。最后在ADS中利用谐波平衡法对倍频器电路进行优化。仿真结果表明,当输入功率为20 dBm时,在80 GHz～100 GHz范围内,输出功率十分平稳,约为5 dBm。     

基于肖特基阻性二极管的140 GHz二倍频器

介绍了一种基于肖特基阻性Z-极管的140GHzZ-倍频器,该倍频器采用矩形波导内嵌石英基片微带电路,通过四肖特基结正向并联结构提高驱动功率承受能力。倍频设计中应用了自建精确二极管三维电磁模型、宽带电磁耦合结构和宽带阻抗匹配结构,以提高仿真结果和实际器件的吻合度。测试结果表明：在频率为65GHz一75GHz,功率为20dBm的驱动信号激励下,二倍频器输出频率为130GHz～150GHz,输出功率为3．3dBm～8．0dBm,倍频损耗为11．7dB～16．3dB。在23dBm-24dBm的最大驱动功率激励下,倍频器最大输出功率达11．2dBm／136GHz,基本达到了成像雷达的应用性能指标。     

一种36 GHz CMOS毫米波三倍频器

针对传统三倍频器输出功率和匹配性能差的问题,基于TSMC0.18μm CMOS工艺,提出一种用滤波器作为匹配电路的三倍频器.该三倍频器输出匹配性能好、功率损耗小,提高了三次谐波的输出功率.对晶体管静态特性进行分析,进一步提升输出功率.流片后的实测结果表明,在31.5～36 GHz输出频率范围内,输入功率为0 dBm时,...     

GaAs pHEMT工艺6～18GHz有源倍频器MMIC

基于GaAs pHEMT工艺,设计了一个6～18 GHz宽带有源倍频器MM IC,最终实现了较高的转换增益和谐波抑制特性。芯片内部集成了输入匹配、有源巴伦、对管倍频器和输出功率放大器等电路。外加3.5 V电源电压下的静态电流为80 mA;输入功率为6 dBm时,6～18 GHz输出带宽内的转换增益为6 dB;基波和三次谐波抑制30 dBc。当输出频率为12 GHz时,100 kHz频偏下的单边带相位噪声为-143 dBc/Hz。芯片面积为1 mm×1.5 mm。     

宽带毫米波四倍频器

对毫米波宽带四倍频器的设计方法并进行了理论分析及计算仿真。介绍了利用平衡式结构对奇次谐波进行抑制,从而实现宽带偶次倍频的原理,提出了选择肖特基二极管的原则。利用HFSS仿真和优化电路结构,采用微带线鳍线结构实现了宽频带的毫米波二倍频器。在此基础上,采用两级倍频的方式实现了宽带毫米波四倍频器。设计的Ka波段毫米波四倍频器输入频率6.625～10 GHz,输入功率为10 dBm时,在26.5～40 GHz频率范围内,输出功率大于10 dBm,对三次和五次谐波的抑制大于20 dBc。     

一种螺旋巴伦结构的毫米波二倍频器MMIC设计

基于GaAs肖特基二极管工艺,研制了一款无源毫米波二倍频器单片微波集成电路(MMIC).该电路的拓扑结构包含并联二极管对,输入巴伦和输入、输出匹配电路,其中输入巴伦为螺旋型Marchand巴伦,使电路输入输出端具有奇偶次谐波相互隔离的特点,不仅抑制了输出奇次谐波,而且增加了线间的耦合,显著减小了芯片的面积.在设计软件对电路进行仿真优化的基础上,经过实际流片并对芯片进行了测试,实现了输入功率为15 dBm时,输出频率在44～60 GHz处,输出功率大于-1 dBm,变频损耗小于16 dB,对基波和各次谐波抑制度大于30 dBc的技术指标.芯片实际尺寸为1.45 mm×1.1 mm.     

无基片空间合成的220 GHz三次倍频电路研究

基于四阳极结同向串联型GaAs平面肖特基二极管,设计并实现了无基片空间合成的220 GHz三次倍频电路。采用四支肖特基二极管协同工作,在脊波导小片上下两侧各倒装焊接两支肖特基二极管,构成上下反向结构。采用场路结合的方式,对倍频电路的倍频效率进行了仿真。仿真结果显示输入功率为300 mW,输出频率为213~229 GHz时,倍频效率大于3%;采用E波段功率放大器推动三次倍频电路,获得了倍频器输出功率。测试数据表明,驱动功率为300 mW时,输出频率为213~229 GHz时,输出功率大于5 dBm,倍频效率为1%~2%。     

W波段功率合成六倍频源

通过倍频方法和功率合成方法设计了W波段六倍频源,将Ku或K波段信号倍频至W波段。信号经过Ka波段二倍频、巴仑、有源放大后,输出两路信号功率约为25 dBm,以此推动变容肖特基二极管进行三倍频,并进行功率合成输出。为了抑制偶次谐波和提高输出功率,二极管使用了反向并联平衡电路结构。该六倍频源在90-115 GHz 输出范围内输出功率大于12 dBm、最大输出功率为13.8 dBm、功率平坦度为1.2 dB。该模块提出了W波段源的产生方法,为今后设计W波段TR组件发射源提供了参考价值。     

Design of a W-band Frequency Tripler for Broadband Operation Based on a Modified Equivalent Circuit Model of GaAs Schottky Varistor Diode

This paper presents the design and experimental results of a W-band frequency tripler with commercially available planar Schottky varistor diodes DBES105a fabricated by UMS, Inc. The frequency tripler features the characteristics of tunerless, passive, low conversion loss, broadband and compact. Considering actual circuit structure, especially the effect of ambient channel around the diode at millimeter wavelength, a modified equivalent circuit model for the Schottky diode is developed. The accuracy of the magnitude and phase of S21 of the proposed equivalent circuit model is improved by this modification. Input and output embedding circuits are designed and optimized according to the corresponding embedding impedances of the modified circuit model of the diode. The circuit of the frequency tripler is fabricated on RT/Rogers 5880 substrate with thickness of 0.127 mm. Measured conversion loss of the frequency tripler is 14.5 dB with variation of ±1 dB across the 75?~?103 GHz band and 15.5?~?19 dB over the frequency range of 103?~?110 GHz when driven with an input power of 18 dBm. A recorded maximum output power of 6.8 dBm is achieved at 94 GHz at room temperature. The minimum harmonics suppression is greater than 12dBc over 75?~?110 GHz band.     

W频段宽带倍频器

介绍了一个W频段宽带倍频器.采用反向并联二极管对结构实现宽带倍频.该倍频器输入为WR-28波导到微带过渡结构,输出为WR-10减高波导.在输入功率为5dBm时,在整个W频段输出功率为0.81±1.80dBm,二次谐波抑制度大于25dBc.该倍频器可把Ka频段的信号源扩展到W频段.     

A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique

A third harmonic enhanced technique is proposed to implement a broadband and low-phase-noise CMOS frequency tripler. It nonlinearly combines a pair of differential fundamental signals to generate deep cuts at the peaks of the fundamental waveform, resulting in a strong third harmonic frequency output. This mechanism has inherent suppression on the fundamental and the other harmonics so that only a low-Q high-pass filter on the lossy silicon substrate is applied at the output to further reject the fundamental and the second harmonic frequencies, in contrast to the high-Q filters used in most of the previous tripler designs. The fabricated circuit using 0.18 m CMOS technology is compact and has an input frequency range from 1.7 GHz to 2.25 GHz, or an output frequency range from 5.1 GHz to 6.75 GHz, resulting in about 28% frequency bandwidth. The optimum conversion loss from the tripler is 5.6 dB (27.5% efficiency) at an input power of 2 dBm. The suppressions for the fundamental, second and fourth harmonics in the measurement are better than 11 dB, 9 dB, and 20 dB within an input power range from 2 dBm to 7 dBm.     

225–255-GHz InP DHBT Frequency Tripler MMIC Using Complementary Split-Ring Resonator

In this paper, a novel design of frequency tripler monolithic microwave integrated circuit (MMIC) using complementary split-ring resonator (CSRR) is proposed based on 0.5-μm InP DHBT process. The CSRR-loaded microstrip structure is integrated in the tripler as a part of impedance matching network to suppress the fundamental harmonic, and another frequency tripler based on conventional band-pass filter is presented for comparison. The frequency tripler based on CSRR-loaded microstrip generates an output power between ?8 and ?4 dBm from 228 to 255 GHz when the input power is 6 dBm. The suppression of fundamental harmonic is better than 20 dBc at 77–82 GHz input frequency within only 0.15?×?0.15 mm² chip area of the CSRR structure on the ground layer. Compared with the frequency tripler based on band-pass filter, the tripler using CSRR-loaded microstrip obtains a similar suppression level of unwanted harmonics and higher conversion gain within a much smaller chip area. To our best knowledge, it is the first time that CSRR is used for harmonic suppression of frequency multiplier at such high frequency band.     

A Novel Quasi-Optical Frequency Multiplier Design for Millimeter and Submillimeter Wavelengths

This paper describes a novel design for millimeter and sub-millimeter wavelength varactor frequency triplers and quadruplers. The varactor diode is coupled to the pump source via waveguide and stripline impedance matching and filtering structures. Output power at the various harmonics of the pump frequency is fed to quasi-optical filtering and tuning elements. The low-loss quasi-optical structures enable near-optimum control of the impedances seen by the varactor diode at the idler and output frequencies, resulting in efficient high-order harmonic conversion. A minimum efficiency of 4 percent with 30-mW input power has been obtained for a tripler operating between 200 and 280 GHz, with a peak efficiency of 8 percent between 250 and 280 GHz. Another tripler, designed for the 260-350-GHz band, gave a minimum conversion efficiency of 3 percent with 30-mW input power, with a peak efficiency of 5 percent at 340 GHz.     

E波段倍频放大模块设计

E波段是毫米波中非常重要的频段,也是较为缺乏研究的频段。E波段可三倍频至亚毫米波频段,其中220 GHz是大气吸收窗口,具有非常重要的研究价值。基于此,文中设计了一款E波段倍频放大模块,为220 GHz太赫兹发射机提供三倍频源信号,该模块输入频率为11.1~13.34 GHz,输出频率为66.6~80 GHz,输入功率为4~5 dBm,输出功率>18 dBm,增益>13 dB,具有较好的输出功率平坦度。该模块的成功研制为亚毫米波收发模块提供了功率源条件。