碳化硅CMOS反相器的特性

建立了6H-SiC CMOS反相器的电路结构和物理模型,并利用MEDICI软件对其特性进行了模拟.研究了SiC CMOS反相器的温度特性,结果表明,室温下沟道长度为1.5μm的6H-SiC CMOS反相器的阈值电压、高电平噪声容限和低电平噪声容限分别为1.657,3.156和1.470V,且随着温度的升高而减小.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

N型6H-SiCMOS电容的电学特性

在可商业获得的 N型 6 H- Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,制备 MOS电容 .详细测量并分析了 6 H- Si C MOS电容的电学特性 ,其有效电荷密度为 4.3× 10 1 0 cm- 2 ;Si C与 Si O2 之间的势垒高度估算为 2 .6 7e V;Si C热生长 Si O2 的本征击穿场强 (用累计失效率 5 0 %时的场强来计算 )为 12 .4MV/ cm ,已达到了制作器件的要求 .     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6 H- Si C肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

6H-SiC MOS场效应晶体管的研制

报道了多晶硅栅 6 H- Si C MOS场效应器件的制造工艺和器件性能。 6 H- Si C氧化层的SIMS分析说明在氧化过程中 ,多余的 C以 CO的形式释放 ,铝元素逸出极少 ,氧化层中因有较多的铝而正电荷密度较大 ,Si C的氧化速率和掺杂类型关系不大。器件漏电流都有很好的饱和特性 ,最大跨导为 0 .36 m S/ mm ,沟道电子迁移率约为 14cm2 / V.s,但串联电阻效应明显。     

SiGe CMOS结构模拟分析

提出一种新的SiGe CMOS结构,用Medici软件对该结构进行二维模拟,分析应变SiGe层、弛豫SiGe层中Ge组份,δ层掺杂浓度以及Si"帽"层厚度等结构参数对SiGe CMOS电学性能的影响.最后,给出该结构组成的反相器传输特性模拟结果.     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

6-T CMOS SRAM单元稳定性分析及设计优化

介绍了一种由两个交叉耦合反向器构成的6-晶体管(6-T)存储单元的噪声容限分析方法.对6-T CMOS SRAM单元的稳定性作了分析及仿真.借助SPICE和MATLAB工具,对存储单元在数据保持和数据读取时的稳定性、数据写入过程中的可靠性及其之间的关系进行了深入研究.对可能影响噪声容限的因素,如单元比、上拉比、MOS管的阈值电压、位线预充电压、电源电压以及温度进行了仿真讨论,并从中得到合适的电路设计参数.流片结果表明,理论分析与实测数据相符.分析数据对基于CSMC O.5μm CMOS工艺的SRAM电路设计优化具有指导作用.     

高可靠性标准单元库性能参数的设计研究

为了设计高可靠性标准单元库的性能参数,需要对其最基本的单元模块反相器的性能参数进行研究。平衡考虑延时特性、噪声容限和功耗等方面的因素,首先确定反相器晶体管PMOS和NMOS的宽度比,然后根据设计需要确定具体的晶体管尺寸,提出了一套完整的确定反相器最小尺寸的方案。最后搭建一组逻辑电路验证所设计的反相器在延时特性和功耗方面体现出的优势,为深亚微米和纳米级标准单元库参数设计提供一定的依据。     

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

The effects of negative bias temperature instability (NBTI) on the performance of a CMOS inverter have been investigated by means of both simulation and experimental methods. The simulation of NBTI effects on CMOS inverter has been done by shifting the pFET V_tho BSIM parameter. The results show that NBTI shifts the inverter transfer curve, reduces the low noise margin and current consumption but increases the high noise margin. A good agreement between simulation and experimental results has been obtained. Therefore, it can be assumed that the effect of NBTI on CMOS circuits can be mainly predicted by shifting the V_tho pFET parameter.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Impact of twin-gate concept on silicon-on-insulator inverters

The low-temperature DC transfer characteristics of inverters, fabricated in a 1 μm silicon-on-insulator (SOI) CMOS technology, are investigated. As will be shown, the operation parameters, such as the noise margin, are degraded by the floating body effects, typical for a partially depleted technology and by low-temperature artefacts. However, by using the so-called twin-gate concept, considerable improvement in the inverter performance can be obtained, both at room temperature and at 4.2 K     

Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits

This paper investigates in detail the basic mechanisms of hysteretic delay and noise margin variations for floating-body partially depleted SOI CMOS domino circuits. We first consider the ‘clock cycling scenario’, which completely eliminates (or isolates) the hysteresis effect of the output inverter, thus allowing one to observe and understand the hysteresis effect of the front-end domino logic stage. Three cases, based on whether the input signals are domino input signals, from other domino circuits, static input signals, from static circuits or latches; or a combination of domino and static input signals, are examined and differentiated. It is shown that hysteretic delay variation is the largest and the noise margin worst for the case with mixed domino and static input signals. Although the delay and noise margin disparities among the three types of input signals are significant at the beginning of the clock cycles, they converge as the circuit approaches steady state. The ‘data cycling scenario’ with the combined hysteresis effect of both the front-end domino logic stage and the output inverter is then discussed. Circuits operating under the ‘data cycling scenario’ are shown to have less body charge loss through the switching cycles than under the ‘clock cycling scenario’.     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

Monolithic CMOS digital integrated circuits in 6H-SiC using animplanted p-well process

We report the first p-well Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits in 6H-SiC. Enhancement mode NMOSFET's and PMOSFET's are fabricated on implanted p-wells and n-type epilayers, respectively. CMOS logic circuits such as inverters, NAND, NOR, XOR, flip-flops, half adders, and 11-stage ring oscillators are implemented using these devices and operated at room temperature, The inverters show stable operation at room temperature and 300°C with V_dd=10 and 15 V     

CMOS反相器低频噪声模型及可靠性表征研究

为了表征CMOS反相器的可靠性,从其负载电流和输出电压的特性入手,详细推导了一种基于载流子波动理论的低频噪声模型,并由实验数据验证了模型的准确性.由实验结果可知,负载电流功率谱密度随频率的增加而减小,遵循1/f噪声的变化规律;得到了负载电流归一化噪声功率谱密度与器件尺寸的关系.通过深入研究1/f 噪声与界面态陷阱密度的关系,验证了1/f噪声可用于表征CMOS反相器的可靠性,证明了噪声幅值越大,器件可靠性越差,失效率显著增大,为评价CMOS反相器的靠性提供了一种可行及有效的方法.     

Low-threshold AlGaN-GaN heterostructure field effect transistorsfor digital applications

The fabrication of an AlGaN-GaN based digital inverter circuit is reported, in which a large gain (up to 180) and a noise margin of ~0.5V have been obtained. The measured temperature coefficient of the switching voltage of the inverter was ~3.5 mV/°C up to 90°C. The simulations predict that such an inverter should operate up to ~230°C     

An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

In modern microprocessors, the multi-port register file is one of the key modules which provides fast and multiple data access for instructions. As the number of access ports in register files increases, stability becomes a key issue due to the voltage fluctuation on bit lines. We propose to apply an isolated inverter to address the voltage fluctuation. To assess the register stability, we derive a closed-form expression of static noise margin (SNM) for our register file. The proposed SNM model can be used as a guideline to predict the impact of several register parameters on the stability and optimize register file designs. To validate the proposed SNM model, we fabricated a test chip of two-write-four-read (2W4R) 1024 bits register file in a TSMC 65 nm low-power CMOS technology. The experimental result shows that the stability of our register file cells with an isolated inverter improve the conventional cells by approximately 2.4 times. Also, the supply voltage causes a fluctuation of SNM of about 65%, while temperature and transistor mismatch cause a fluctuation of SNM of about 20%.     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。