RNS-FPL merged architectures for orthogonal DWT

Novel, regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1D discrete wavelet transform (DWT) and 1D inverse discrete wavelet transform (1DWT) are presented. These structures halve the number of look-up tables (LUTs) required per octave, providing a sustained throughput independent of the input data and filter coefficient precision. They are suitable to be considered as the core of 2D DWT processors for high data rate image processing applications     

Computation of DWT via FHT-based implementation

It is well known that most wavelet transform algorithms compute sampled coefficients of the continuous wavelet transform using the filter bank structure of the discrete wavelet transform (DWT). Although this method is efficient, noticeable computational savings have been obtained through an FFT-based implementation. The authors present a fast Hartley transform (FHT)-based implementation of the filter bank and show that noticeable overall computational savings can be obtained     

Speech frame recognition based on less shift sensitive wavelet filter banks

The wavelet transform possesses multi-resolution property and high localization performance; hence, it can be optimized for speech recognition. In our previous work, we show that redundant wavelet filter bank parameters work better in speech recognition task, because they are much less shift sensitive than those of critically sampled discrete wavelet transform (DWT). In this paper, three types of wavelet representations are introduced, including features based on dual-tree complex wavelet transform (DT-CWT), perceptual dual-tree complex wavelet transform, and four-channel double-density discrete wavelet transform (FCDDDWT). Then, appropriate filter values for DT-CWT and FCDDDWT are proposed. The performances of the proposed wavelet representations are compared in a phoneme recognition task using special form of the time-delay neural networks. Performance evaluations confirm that dual-tree complex wavelet filter banks outperform conventional DWT in speech recognition systems. The proposed perceptual dual-tree complex wavelet filter bank results in up to approximately 9.82 % recognition rate increase, compared to the critically sampled two-channel wavelet filter bank.     

A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting

The filter bank approach for computing the discrete wavelet transform (DWT), which we call the convolution method, can employ either a nonpolyphase or polyphase structure. This work compares filter banks with an alternative polyphase structure for calculating the DWT-the lifting method. We look at the traditional lifting structure and a recently proposed "flipping" structure for implementing lifting. All filter bank structures are implemented on an Altera field-programmable gate array. The quantization of the coefficients (for implementation in fixed-point hardware) plays a crucial role in the performance of all structures, affecting both image compression quality and hardware metrics. We design several quantization methods and compare the best design for each approach: the nonpolyphase filter bank, the polyphase filter bank, the lifting and flipping structures. The results indicate that for the same image compression performance, the flipping structure gives the smallest and fastest, low-power hardware.     

一种二维离散子波变换的滤波器结构

子波变换具有良好的时间（空间）频率局部化性能，在图象子带编码中二维离散子波变换是一种接近理想的子带分析／综合子系统．本文提出一种利用一维离散子波变换实现二维有限长离散子波变换的方法，同时给出了二维离散子波正变换（DWT）和反变换（IDWT）的滤波器实现结构．实验结果表明新的方法具有良好的重构性，完全适用于图象压缩编码系统中的分析／综合子系统．     

VLSI implementation of discrete wavelet transform

This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N×10⁶ samples/s corresponding to a clock speed of N MHz     

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform

A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages are performed concurrently for transposition-free implementation of 2-D DWT. The proposed design can offer nearly the same throughput rate, and requires the same or less the number of adders and multipliers as the best of the existing structures. The storage space is found to occupy most of the area in the existing 2-D DWT structures but the proposed structure does not require any on-chip or off-chip storage of input samples or storage/transposition of intermediate output. The proposed one, therefore, involves considerably less hardware complexity compared with the existing structures. Apart from that, it has less duration of cycle period in comparison to the existing structures, and has a latency of cycles while all the existing structures have latency of cycles, the filter order being small compared to the input size .     

The recursive pyramid algorithm for the discrete wavelet transform

The recursive pyramid algorithm (RPA) is a reformulation of the classical pyramid algorithm (PA) for computing the discrete wavelet transform (DWT). The RPA computes the N-point DWT in real time (running DWT) using just L(log N-1) words of storage, as compared with O(N) words required by the PA. L is the length of the wavelet filter. The RPA is combined with the short-length FIR filter algorithms to reduce the number of multiplications and additions     

Simplified biorthogonal discrete wavelet transform for VLSI architecture design

Biorthogonal discrete wavelet transform (BDWT) has gained general acceptance as an image processing tool. For example, the JPEG2000 standard is completely based on the BDWT. In BDWT, the scaling (low-pass) and wavelet (high-pass) filters are symmetric and linear phase. In this work we show that by using a specific sign modulator the BDWT filter bank can be realized by only two biorthogonal filters. The analysis and synthesis parts use the same scaling and wavelet filters, which simplifies especially VLSI designs of the biorthogonal DWT/IDWT transceiver units. Utilizing the symmetry of the scaling and the wavelet filters we introduce a fast convolution algorithm for implementation of the filter modules. In multiplexer–demultiplexer VLSI applications both functions can be constructed via two running BDWT filters and the sign modulator. This work was supported by the National Technology Agency of Finland (TEKES).     

Parallel pipeline implementation of wavelet transforms

Wavelet transforms have been one of the important signal processing developments in the last decade, especially for applications such as time-frequency analysis, data compression, segmentation and vision. Although several efficient implementations of wavelet transforms have been derived, their computational burden is still considerable. The paper describes two generic parallel implementations of wavelet transforms, based on the pipeline processor farming methodology, which have the potential to achieve real-time performance. Results show that the parallel implementation of the oversampled wavelet transform achieves virtually linear speedup, while the parallel implementation of the discrete wavelet transform (DWT) also outperforms the sequential version, provided that the filter order is large. The DWT parallelisation performance improves with increasing data length and filter order, while the frequency-domain implementation performance is independent of wavelet filter order. Parallel pipeline implementations are currently suitable for processing multidimensional images with data length at least 512 pixels     

Discrete Lattice Wavelet Transform

The discrete wavelet transform (DWT) has gained a wide acceptance in denoising and compression coding of images and signals. In this work we introduce a discrete lattice wavelet transform (DLWT). In the analysis part, the lattice structure contains two parallel transmission channels, which exchange information via two crossed lattice filters. For the synthesis part we show that the similar lattice structure yields a perfect reconstruction (PR) property. The PR condition can be used to design half-band filters, which effectively eliminate aliasing in decimated tree structured wavelet transform. The DLWT can be implemented directly to any of the existing DWT algorithms     

Perceptual Audio Coding Using Sinusoidal/Optimum Wavelet Representation

A perceptual audio coder, in which each audio segment is adaptively analyzed using either a sinusoidal or an optimum wavelet basis according to the time-varying characteristics of the audio signals, has been constructed. The basis optimization is achieved by a novel switched filter bank scheme, which switches between a uniform filter bank structure (discrete cosine transform) and a non-uniform filter bank structure (discrete wavelet transform). A major artifact of the International ISO/Moving Pictures Experts Group (MPEG) audio coding standard (MPEG-I layers 1 and 2) known as pre-echo distortion which uses a uniform filter bank structure for audio signal analysis, is almost eliminated in the proposed coder. A perceptual masking model implemented using a high-resolution wavelet packet filter bank with 27 subbands, closely mimicking the critical bands of the human auditory system, is employed in this audio coder. The resulting scheme is a variable bit-rate audio coder, which provides compression ratios comparable to MPEG-I layers 1 and 2 with almost transparent quality.     

Time-domain design of low delay wavelet transforms

The authors use a time-domain design methodology previously used for perfect reconstruction filter banks to design wavelet prototypes which may be used to generate the discrete wavelet transform (DWT). An advantage of this method is the significant reduction in the inherent delay, and consequent reduction in the number of multiplications required to implement the DWT. It is proposed that these low delay wavelets will find applications in time critical systems.<>     

海杂波背景下利用DWT提高MTD性能的仿真分析

针对利用传统的窄带滤波器组实现海杂波背景下动目标检测（MTD）时,副瓣电平往往过高这一问题,讨论了离散小波变换（DWT）在MTD中的应用。在瑞利型海杂波背景下,通过对MTD所得到的结果进行小波变换,可以达到提高雷达系统处理增益的同时,降低系统输出的副瓣电平。最后,分别利用Haar小波和db2小波进行了仿真实验,结果证明该方法可以有效地提高MTD性能。     

一种小波分解滤波器高速实现结构

近年来,小波变换得到了广泛的应用,快速塔式分解算法是它应用的一个有利工具,其地位相当于FFT之于Fourier分析,因此DWT的快速硬件实现变成了其应用的一个重要问题,本文通过将并行systolic FIR滤波器结构引入小波分解滤波器的设计,得到了一种小波分解滤波器的实现结构。该结构由于应用了systolic技术及采用并行结构,除了可以提高运算速度外,还可以提高系统的数据吞吐率以及降低系统功耗。     

2D DWT VLSI architecture for wavelet image processing

A cost-effective VLSI architecture with separate data-paths and their corresponding filter structure is proposed for performing a two-dimensional discrete wavelet transform (2D DWT). Compared with the conventional 2D DWT VLSI architectures, the proposed semi-recursive 2D DWT VLSI architecture has minimum hardware cost, and optimised data-bus utilisation, scheduling control overhead and storage size     

基于采样二通道不可分小波的多光谱图像融合

针对基于非下采样不可分小波图像融合方法空间分辨率不高、基于张量积小波融合方法会出现方块效应的不足,提出了一种基于伸缩矩阵为[1,1;1,-1]的二通道采样不可分小波的多光谱图像和全色图像融合方法.利用矩阵扩充方法,构造了一组新的不可分低通滤波器和高通滤波器组,利用所设计滤波器组分别对多光谱图像的亮度分量和全色图像作下采样的多尺度不可分小波分解,分别对分解后的低频子图像和高频子图像按不同的融合规则进行融合.实验结果表明,其保持光谱信息的能力和保持空间分辨率信息的能力比基于IHS变换融合方法、基于DWT的融合方法、基于IHS-DWT的融合方法、基于IHS-Contourlet变换的融合方法、基于IHS-Curvelet变换的融合方法、SRF方法都强,与基于非下采样的二通道不可分正交小波和不可分双正交小波融合方法相比,该方法能保持较好的整体光谱信息和较高的空间分辨率信息.     

9/7提升小波变换图像处理算法的高速FPGA实现

提升结构(Lifting Scheme)是一种新的双正交小波变换构造方法.这种方法使得计算复杂度大大降低,有效地减少了运行时间.介绍了基于FPGA的高速9/7提升小波变换的设计,提出采用多级流水线硬件结构实现一维离散小波变换(1-D DWT).该结构使系统吞吐量提高到原来的3倍,面积仅增加40%.在实现二维离散小波变换(2-D DWT)时采用基于行的结构,可以提高片内资源利用率和运行速度,满足小波变换实时性的要求.     

A translation- and scale-invariant adaptive wavelet transform

This paper presents a new approach to deal with the translation- and scale-invariant problem of the discrete wavelet transform (DWT). Using a signal-dependent filter, whose impulse response is calculated by the first two moments of the original signal and a scale function of an orthonormal wavelet, we adaptively renormalized a signal. The renormalized signal is then decomposed by using the algorithm of the conventional DWT. The final wavelet transform coefficients, called adaptive wavelet invariant moments (AWIM), are proved to be both translation- and scale-invariant. Furthermore, as an application, we define a new textural feature in the framework of our adaptive wavelet decomposition, show its stability to shift and scaling, and demonstrate its efficiency for the task of scale-invariant texture identification.     

基于DSP的正交离散子波变换系统的设计与实现

子波变换现已成为一种重要的信号处理方法．本文提出一种以ＴＩ公司ＤＳＰ（ＴＭＳ３２０Ｃ３０）为基础的一维正交离散子波变换系统的实现方法，用该系统实现 Ｍａｌｌａｔ 正交子波快速分解与重构算法，并详细介绍了该系统的电路设计原理和相应的软件流程．测试结果表明该系统重构信号的绝对误差小于１０~( －３)。