Improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

An improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region was proposed. The recessed source/drain drift region is to reduce channel thickness between gate and drain as well as eliminate gate depletion layer extension to source/drain. The recessed source/drain drift region of the proposed structure can be realized with the formation of double-recessed gate region. The simulated results showed that the breakdown voltage of the proposed structure is 145 V compared to 109 V of that of the published 4H-SiC MESFETs with double-recessed gate structure and yet maintain almost same saturation drain current characteristics. The output power density of the proposed structure is about 33% larger than that of the published double-recessed gate structure. The cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of the proposed structure are 21.8 GHz and 81.5 GHz compared to 19.0 GHz and 76.4 GHz of that of the published double-recessed gate structure, respectively.     

AlGaN/GaN self-aligned MODFET with metal oxide gate for millimeter wave application

As promising candidates for future microwave power devices, GaN-based high-electron mobility transistors (HEMTs) have attracted much research interest. An investigation of the operation of AlGaN/GaN n type self-aligned MOSFET with modulation doped GaN channels is presented. Liquid phase deposited (LPD) SiO₂ is used as the insulating material. An analytical model based on modified charge control equations is developed. The investigated critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak DC trans-conductance (g_m), break down voltage (V_br) and unity current gain cut-off frequency (f_T). The typical DC characteristics for a gate length of 1 μm with 100 μm gate width are following: I_max=800 mA/mm, V_break-down=50 V, g_{m_extrinsic}=200 mS/mm, V_pinchoff=−10 V. The analysis and simulation results on the transport characteristics of the MOS gate MODFET structure is compared with the previously measured experimental data. The calculated values of f_T (20-130 GHz) suggest that the operation of the proposed device effectively, has sufficiently high current gain cutoff frequencies over a wide range of drain voltage, which is essential for high-power performance at microwave frequencies. The proposed device offers lower on-state resistance. The results so obtained are in close agreement with the experimental data.     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

InAs/AlSb HEMTs for cryogenic LNAs at ultra-low power dissipation

Properties of the InAs/AlSb high electron mobility transistor, essential for the design of a cryogenic low-noise amplifier (LNA) operating at low power dissipation, have been studied. Upon cooling from 300 K to 77 K, the dc transconductance g_m was enhanced by 30% at a drain-source voltage V_DS of 0.1 V. The gate current leakage showed a strong reduction of the Schottky current component at 77 K. Compared to 300 K, the cut-off frequency f_T and maximum oscillation frequency f_max showed a significant improvement at 77 K with a peak f_T (f_max) of 167 (142) GHz at V_DS = 0.2 V. The suitability of the Sb HEMT for a cryogenic LNA design up to 50 GHz, operating at low dc power dissipation, was investigated through the extraction of the NF_tot,min figure of merit. It was found that the best device performance in terms of noise and gain is achieved at a low V_DS of 0.16 V resulting in a minimum NF_tot,min of 0.6 dB for a frequency of 10 GHz when operating at 77 K. A benchmarking between the Sb HEMT and an InP HEMT has been conducted highlighting the device improvement in noise and gain required to reach today’s state-of-the-art cryogenic LNAs.     

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In_0.7Ga_0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f_T) of 113 GHz and a maximum oscillation frequency (f_max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm² device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.     

High breakdown voltage 4H-SiC MESFETs with floating metal strips

A high breakdown voltage 4H-SiC MESFET with floating metal strips (FMS) was proposed. The maximum electrical field of the MESFET gate is clamped after surface depletion layer punch through to FMS. The optimized results showed that the breakdown voltage of the 4H-SiC MESFET with two strips and one strip are 180% and 95% larger than that of the conventional one without FMS and meanwhile maintain almost same saturation drain current. The maximum theoretical output power density of the 4H-SiC MESFET with two strips and one strip are 14.5 W and 10.0 W compared to 4.8 W of the conventional structure. The cut-off frequency (f_T) of 14.7 GHz and 15.6 GHz and the maximum oscillation frequency (f_max) of 44.8 GHz and 48.7 GHz for the 4H-SiC MESFET with two strips and one strip are obtained respectively, which is just a little bit lower than that of the conventional structure.     

A new small-signal MOSFET model and parameter extraction method for RF IC's application

In this paper, an accurate and simple small signal model of RF MOSFETs accounting for the distributed gate effect, the substrate parasitics and charge conservation is proposed. Meanwhile, a direct and accurate extraction method using linear regression approach for the components of the equivalent circuit of the MOSFET with S-parameters analysis is also proposed. The proposed model and extraction method are verified with the experimental data and an excellent agreement is obtained up to 10 GHz. The extraction results from the measured data for various bias conditions are presented. Also, the extracted parameters, such as transconductance g_m, match well with those obtained from DC measurements. Besides, it is shown that a significant error in circuit performances would be found if the charge conservation is not properly considered.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Power performance and scalability study of AlGaAs/GaAs double-recessed pseudomorphic high electron mobility transistors on unthinned substrate for coplanar waveguide circuit applications

We have investigated the power performance and scalability of AlGaAs/GaAs Double-Recessed Pseudomorphic High Electron Mobility Transistors (DR-PHEMTs) at 10 GHz on an unthinned GaAs substrate for CoPlanar Waveguide (CPW) circuit applications. It was found that the output power varied linearly with the logarithm of the device’s gate width ranging from 200 to 1000 μm. It increased at a rate of 0.01 dB/μm. That worked out to a doubling of output power (or 3 dB) for every 300 μm increase in the gate width. Gain decreased at a rate of about 0.005 dB/μm while PAE generally improved when the gate width was increased. As for DC measurement, the maximum transconductance of the device was about 375 mS/mm at V_G = −0.5 V and V_DS = 3 V. The gate-drain breakdown voltage (BV_GD) measured was −20 V, defined at I_G = −1 mA/mm. The microwave performance of the devices was measured on-wafer using a load-pull system at a bias of V_G = −0.5 V and V_DS = 8 V. For a device with a gate width of 1 mm, its saturated CW output power, gain and PAE value at 10 GHz was 27.5 dBm (0.55 W), 8 dB and 48%, respectively. At this same set of bias conditions, the value of f_t and f_max was 40 and 80 GHz, respectively.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Record gain at 3.1 GHz of 4H-SiC high power RF MESFET

In this paper, a very high gain 4H-SiC power MESFET with incorporation of L-gate and source field plate (LSFP-MESFET) structures for high power and RF applications is proposed. The influence of L-gate and source field plate structures on saturation current, breakdown voltage (V_b) and small-signal characteristics of the LSFP-MESFET was studied by numerical device simulation. The optimized results showed that V_b of the LSFP-MESFET is 91% larger than that of the 4H-SiC conventional MESFET (C-MESFET), which meanwhile maintains almost 77% higher saturation drain current characteristics. The maximum output power densities of 21.8 and 5.5 W/mm are obtained for the LSFP-MESFET and C-MESFET, respectively, which means about 4 times larger output power for the proposed device. Also, the cut-off frequency (f_T) of 23.1 GHz and the maximum oscillation frequency (f_max) of 85.3 GHz for the 4H-SiC LSFP-MESFET are obtained compared to 9.4 and 36.2 GHz for that of the C-MESFET structure, respectively. The proposed LSFP-MESFET shows a new record maximum stable gain exceeding 22.7 dB at 3.1 GHz, which is 7.6 dB higher than that of the C-MESFET. To the best of our knowledge, this is 2.5 dB greater than the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

A low-power, high-frequency, all-NMOS all-current-mirror sinusoidal quadrature oscillator

A low-power, high-frequency, sinusoidal quadrature oscillator is presented through the use of only current mirrors where the small-signal paths are realized through all NMOS transistors. The technique is relatively simple based on (i) inherent time constant of current mirrors, i.e. the internal capacitances and the transconductance of a diode-connected NMOS, (ii) a negative resistance formed by a transconductance of a diode-connected NMOS load of a current mirror. No external passive components are required. As a particular example, a 2.83 GHz, 0.374 f_T, 0.38 mW sinusoidal quadrature oscillator is demonstrated. Total harmonic distortions are less than 0.8%. The oscillation frequency is current-tunable over a range of 640 MHz or 22.62%. The amplitude matching and the quadrature phase matching are better than 0.04 dB and 0.17°, respectively. A figure of merit called a normalized carrier-to-noise ratio is 158.23 dBc/Hz at the 2 MHz offset from 2.83 GHz. Comparisons to other approaches are also presented.     

Buried-Pt gate InP/In0.52Al0.48As/In0.7Ga0.3As pseudomorphic HEMTs

InP-based high electron mobility transistors (HEMTs) were fabricated by depositing Pt-based multilayer metallization on top of a 6-nm-thick InP etch stop layer and then applying a post-annealing process. The performances of the fabricated 55-nm-gate HEMTs before and after the post-annealing were characterized and were compared to investigate the effect of the penetration of Pt through the very thin InP etch stop layer. After annealing at 250 °C for 5 min, the extrinsic transconductance (G_m) was increased from 1.05 to 1.17 S/mm and Schottky barrier height was increased from 0.63 to 0.66 eV. The unity current gain cutoff frequency (f_T) was increased from 351 to 408 GHz, and the maximum oscillation frequency (f_max) was increased from 225 to 260 GHz. These performance improvements can be attributed to penetration of the Pt through the 6-nm thick InP layer, and making contact on the InAlAs layer. The STEM image of the annealed device clearly shows that the Pt atoms contacted the InAlAs layer after penetrating through the InP layer.     

A SiGe HBT low noise amplifier using on-chip notch filter for K band wireless communication

In this paper a new notch filter topology has firstly been described. In order to improve the input match as well as enhance the gain on the operating frequency of 20.5 GHz, extra capacitor has firstly been added in the passive base-collector notch filter forming a new scheme, eliminating the operating-frequency (op) input mismatch in formal base-collector notch filters. EM simulations have shown that the LNA obtained 14.1 dB gain at 20.5 GHz and high image-rejection ratio (IRR) of 33.5 dB at image frequency of 15 GHz, and S₁₁ of -15 dB was obtained compared to −8 dB without notch filter at operating frequency, NF was below 5 dB at gain peak frequency, power consumption was 18 mW at 3 V voltage supply, and IIP3 was 3.43 dBm ensuring a high linearity in SiGe bipolar process.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

A Comparative Study of a Dielectric‐Defined Process on AlGaAs/InGaAs/GaAs PHEMTs

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric‐defined process. This process was utilized to fabricate 0.12 μm × 100 µm T‐gate PHEMTs. A two‐step etch process was performed to define the gate footprint in the SiN_x. The SiN_x was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T‐gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross‐sectional area of the gate and its mechanically stable structure. From s‐parameter data of up to 50 GHz, an extrapolated cut‐off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the SiN_x) with sample A (dry etching for the SiN_x), we observed an 62.5% increase of the cut‐off frequency. This is believed to be due to considerable decreases of the gate‐source and gate‐drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.     

Analysis of electrical characteristics of Au/SiO2/n-Si (MOS) capacitors using the high-low frequency capacitance and conductance methods

The purpose of this paper is to analyze electrical characteristics in Au/SiO₂/n-Si (MOS) capacitors by using the high-low frequency (C_HF-C_LF) capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements have been carried out in the frequency range of 1 kHz-10 MHz and bias voltage range of (−12 V) to (12 V) at room temperature. It was found that both C and G/ω of the MOS capacitor were quite sensitive to frequency at relatively low frequencies, and decrease with increasing frequency. The increase in capacitance especially at low frequencies is resulting from the presence of interface states at Si/SiO₂ interface. Therefore, the interfacial states can more easily follow an ac signal at low frequencies, consequently, which contributes to the improvement of electrical properties of MOS capacitor. The interface states density (N_ss) have been determined by taking into account the surface potential as a function of applied bias. The energy density distribution profile of N_ss was obtained from C_HF-C_LF capacitance method and gives a peak at about the mid-gap of Si. In addition, the high frequency (1 MHz) capacitance and conductance values measured under both reverse and forward bias have been corrected for the effect of series resistance (R_s) to obtain the real capacitance of MOS capacitors. The frequency dependent C-V and G/ω-V characteristics confirm that the N_ss and R_s of the MOS capacitors are important parameters that strongly influence the electrical properties of MOS capacitors.     

SiC衬底上栅长70 nm fT / fmax >160 GHz的InAlN/GaN HEMTs器件

在SiC衬底上制备了InAlN/GaN 高电子迁移率晶体管（HEMTs）,并进行了表征。为提高器件性能,综合采用了多种技术,包括高电子浓度,70 nm T型栅,小的欧姆接触电阻和小源漏间距。制备的InAlN/GaN器件在栅偏压为1 V时得到的最大饱和漏电流密度为1.65 A/mm,最大峰值跨导为382 mS/mm。70 nm栅长器件的电流增益截止频率fT和最大振荡频率fmax分别为162 GHz和176 GHz。     

A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.