适用于高品质射频集成电感的多孔硅新型衬底制备技术

提出了背向选区腐蚀生长多孔硅的集成电感衬底结构.ASITIC模拟证明,该新型衬底结构的集成电感在高频下仍具有较高的品质因子.采用此工艺,在固定腐蚀液配比的条件下,变化电流密度和阳极氧化时间,制备出了高质量的厚膜多孔硅,并测量了多孔硅的生长厚度、孔径大小和表面形貌,得出了多孔硅生长速率随阳极氧化时间和电流密度的变化关系,为背向选区腐蚀工艺制备高品质硅基集成电感奠定了理论和实验基础.     

硅基底电子束蒸发铝膜阳极氧化特性

研究了硅衬底上电子束蒸发铝膜,在H2SO4水溶液中阳极氧化形成硅衬底多孔氧化铝复合结构的过程.硅衬底电子束蒸发铝膜的阳极氧化过程主要由多孔氧化铝的生长、氧化铝生长向氧化硅生长的过渡和氧化硅生长三个阶段构成.硅衬底多孔氧化铝复合结构的透射电子显微镜观察表明,在硅衬底上形成了垂直于硅表面的氧化铝纳米孔,而孔底可形成SiO2层.有序结构多孔氧化铝的形成不依赖于铝膜的结晶状态,而是由阳极氧化过程的自组织作用所决定的.实验表明将多孔氧化铝制备工艺移植到硅基衬底上直接形成硅基衬底多孔氧化铝复合结构是可行的,它也为硅基纳米材料的制备提供了一种新的自组织模板.     

硅基底电子束蒸发铝膜阳极氧化特性

研究了硅衬底上电子束蒸发铝膜 ,在 H2 SO4 水溶液中阳极氧化形成硅衬底多孔氧化铝复合结构的过程 .硅衬底电子束蒸发铝膜的阳极氧化过程主要由多孔氧化铝的生长、氧化铝生长向氧化硅生长的过渡和氧化硅生长三个阶段构成 .硅衬底多孔氧化铝复合结构的透射电子显微镜观察表明 ,在硅衬底上形成了垂直于硅表面的氧化铝纳米孔 ,而孔底可形成 Si O2 层 .有序结构多孔氧化铝的形成不依赖于铝膜的结晶状态 ,而是由阳极氧化过程的自组织作用所决定的 .实验表明将多孔氧化铝制备工艺移植到硅基衬底上直接形成硅基衬底多孔氧化铝复合结构是可行的     

多孔硅的光致发光谱

本文介绍了用电化学腐蚀的阳极氧化工艺，在硅衬底上制备多孔硅（ＰＳ）薄膜，实验测定了多孔硅薄膜的光致发光谱（ＰＬ），发现光致发光谱峰值波长随阳极氧化时间、ＨＦ浸泡时间或置于空气中自然氧化时间增加而向短方向移动（“蓝移”）．文章用量子限制效应（ＱＣＥ）理论解释了上述实验结果，并提出了在多孔硅发光机制中还存在表面态及实物质在发光中的作用。     

与硅平面工艺兼容的p~-/p~+型多孔硅的发光特性研究

ｐ－／ｐ＋型多孔硅电致发光器件对实现硅基光电子集成具有重要的意义，我们通过改变样品衬底的离子注入浓度和阳极氧化条件，在ｐ－／ｐ＋型单晶硅衬底上生长了不同的多孔硅样品后，在纯氧和稀氧氛围下对样品进行了８００℃高温退火处理．通过测量样品的光致发光谱，研究了样品衬底离子注入浓度，阳极氧化条件及后处理条件等对ｐ－／ｐ＋型多孔硅样品发光的影响，为研制与硅平面工艺兼容的多孔硅发光器件，提供了重要的参考设计参数和进一步改进工艺的依据     

多孔硅微结构与场发射性能研究

采用阳极氧化及阴极还原表面处理技术制备性能稳定的纳米多孔硅薄膜.用原子力显微镜(AFM)表征多孔硅的表面形貌,用扫描电子显微镜(SEM)表征多孔硅的横截面结构.采用场发射测试装置研究了阳极氧化腐蚀时间及等离子表面处理对多孔硅场发射性能影响.结果表明,阳极氧化腐蚀时间越长,所得多孔硅场发射性能越好,相对应的开启电压越低,电流密度越大;等离子处理可有效提高场发射性能,等离子处理后的多孔硅薄膜作为阴极发射材料具有极大的潜能.     

多孔硅的微观结构及其氧化特性

采用ＴＥＭ技术研究了多孔硅微观结构．结果表明：当衬底材料为中等偏高掺杂（０．０３２Ω·ｃｍ）时，多孔硅具有两种不同类型的微观结构，它们的形成和阳极氧化反应电流密度有关．修正了Ｂｅａｌｅ关于多孔硅微观结构的形成模型．采用ＸＰＳ、ＩＲＳ和击穿电压测量，研究了多孔氧化硅的特性，发现多孔硅在低温下（７５０℃）的氧化特性，除了和多孔度有关外，和多孔硅的微观结构以及氧化前的热处理温度有关．     

用于硅衬底隔离的选择性多孔硅厚膜的制备

在硅衬底上形成高阻隔离层对于提高硅基射频电路的性能具有重要意义。采用多孔硅厚膜作为隔离层，能够极大地降低衬底高频损耗。本文对n^ 型硅衬底上选择性多孔硅厚膜的制备进行了研究。通过在阳极氧化反应中采用不同的HF溶液的浓度、电流密度和反应时间来控制多孔硅的膜厚、孔隙度等特性。有效地减少了多孔硅的龟裂失效，得到的多孔硅最大膜厚为72μm。并测量了多孔硅的生长速率与表面形貌。     

微结构制备中选择性多孔硅牺牲层技术的研究

利用多孔硅形成的选择性。在指定的硅衬底区域制作多孔硅作牺牲层，提出了制作微结构，后进行阳极氧化，形成多孔硅牺牲层的工艺，由此制备出了良好的悬空结构，并对多孔硅形成的选择性、掩模材料和工艺条件进行了研究。     

电化学阳极氧化制备多孔硅及其发光性能研究

利用电化学阳极氧化法,通过控制电流密度和电解液的成分,在p型(100)硅衬底上制备了大孔的多孔硅结构,利用X射线衍射仪、扫描电子显微镜和紫外荧光光度计研究了不同条件下制备的多孔硅样品的行貌特征、结构和发光性能。在此基础上进一步考察了对多孔硅样品进行氢氟酸浸泡刻蚀和阴极氢饱和处理对其发光性能的影响。讨论了后处理对多孔硅发光性能影响的机理。     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

Microwave inductors and capacitors in standard multilevelinterconnect silicon technology

Spiral inductors and metal-to-metal capacitors for microwave applications, which are integrated on a silicon substrate by using standard 0.8 μm BiCMOS technology, are described. Optimization of the inductors has been achieved by tailoring the vertical and lateral dimensions and by shunting several interconnect metal layers together. Lumped element models of inductors and capacitors provide detailed understanding of the important geometry and technological parameters on the device characteristics. The high quality factors of nearly 10 for the inductors are among the best results in silicon, particularly when using standard silicon technology     

High-performance inductors on plastic substrate

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.     

Integrated Inductors Modeling for Library Development and Layout Generation

In this work we propose a modification to the conventional lumped equivalent circuit model for integrated inductors. Also the widely used parametric model is modified. The proposed models expand the frequency range where the integrated inductor behavior is accurately predicted. They are useful in developing automatic tools to assist the designers in selecting and automatically laying-out integrated inductors [1]. This work is based on measurements from integrated inductors fabricated in a standard silicon process.     

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si as a thick layer isolating the Si substrate from the metallization in an otherwise standard CMOS technology. We present theoretical designs produced with full-wave Method-of-Moments simulations, verified by measurements in standard 0.18 μm CMOS technology using Al metallization. When porous Si is introduced in that technology, the same inductor metallization produced Q-factor enhancements of the order of 50%, compared to the same inductor on bulk crystalline silicon. We also produce optimized single-ended inductor designs using Cu on porous Si, in a 0.13 μm-compatible CMOS technology. The resulting Q-factors are enhanced by a factor of 2 and reach values of 30 or more in the 2–3 GHz frequency range. Even higher quality factors can be obtained in this technology when differential designs are used.     

Models and Tools for CMOS Integrated Inductors

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.     

Packaging-compatible high Q microinductors and microfilters forwireless applications

To meet requirements in mobile communication and microwave integrated circuits, miniaturization of the inductive components that many of these systems require is of key importance. At present, active circuitry is used which simulates inductor performance and which has high Q-factor and inductance; however, such circuitry has higher power consumption and higher potential for noise injection than passive inductive components. An alternate approach is to fabricate integrated inductors, in which lithographic techniques are used to pattern an inductor directly on a substrate or a chip. However, integrated inductors can suffer from low Q-factor and high parasitic effects due to substrate proximity. To expand the range of applicability of integrated microinductors at high frequency, their electrical characteristics, especially quality factor, should be improved. In this work, integrated spiral microinductors suspended (approximately 60 μm) above the substrate using surface micromachining techniques to reduce the undesirable effect of substrate proximity on the inductor performance are investigated. The fabricated inductors have inductances ranging from 15-40 nH and Q-factors ranging from 40-50 at frequencies of 0.9-2.5 GHz. Microfilters based on these inductors are also investigated by combining these inductors with integrated polymer filled composite capacitors     

陶瓷基板上的集成微电感模型与制作

对陶瓷基板上的集成微电感模型进行了分析.由于陶瓷基板的介电常数比Si基板低,电阻率极高,因此衬底损耗大大减小,从而有效提高了电感的Q值.同时,为了更好进行对比,研究中采用相同工艺在陶瓷基板和Si基板上同批制作了集成电感,两者的结构参数完全一致.测试结果表明,两者的电感值L基本相同,然而陶瓷基板上集成微电感Q值的峰值要比Si基板集成微电感高7左右,Si基板上Q值峰值在5 GHz以下,而陶瓷基板集成微电感的Q值峰值在10 GHz左右.