Production scheduling algorithms for a semiconductor test facility

The authors develop production scheduling algorithms for semiconductor test operations. The operations in the facility under study are characterized by a broad product mix, variable lot sizes and yields, long and variable setup times, and limited test equipment capacity. The approach presented starts by dividing the facility or job shop into a number of work centers. The method then proceeds to sequence one work center at a time. A disjunctive graph representation of the entire facility is used to capture interactions between work centers. The introduction of different management objectives leads to different work center problems and different production scheduling algorithms. The authors present algorithms for two different work center problems. Direction for future research are discussed     

集成芯片的可测性设计技术

主要介绍了三种可测性设计（DFT）技术,分别是：扫描设计（Scan Design）、边界扫描设计（Boundary Scan Design）和内建自测试设计（BIST）。对于这三种设计技术,分别介绍了其原理和设计过程。     

IC quality and test transparency

It is shown that extremely high single-stuck fault coverage is necessary for high-quality products. Even 100% single-stuck fault coverage may not guarantee adequate quality. Results are presented that extend previous work and show that for high required IC quality, process yield has a negligible effect on required test thoroughness. The extensions consist of: removing the assumption of a one-to-one correspondence between chip defects and single-stuck faults; demonstrating that for high quality levels the dependence of quality on test coverage is linear rather than exponential and that for high yields, the dependence of quality on yield is also linear; and showing that the yield used in the calculations should be functional rather than die yield. The theoretical results are compared with data obtained from measurements at a production IC facility     

Defect-oriented test scheduling

As tester complexity and cost increase, reducing test time is an important manufacturing priority. Test time can be reduced by ordering tests so as to fail defective units early in the test process. Algorithms to order tests that guarantee optimality require execution time that is exponential in the number of tests applied. We develop a simple polynomial-time heuristic to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. An ordering algorithm requires information on the ability of tests to detect defective units. One way to obtain this information is by simulation. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this subset is representative. The ordering heuristic was applied to manufactured digital and analog integrated circuits (ICs) tested with commercial testers. When both approaches work, the orders generated by the heuristic are optimal. More importantly, the heuristic is able to generate an improved order for large problem sizes when the optimal algorithm is not able to do so. The new test orders result in a significant reduction, as high as a factor of four, in the time needed to identify defective units. We also assess the validity of using such sampling techniques to order tests     

Optimized desoak system for IC panel test handlers

This paper presents a unique airflow-based thermal system that returns thermally conditioned integrated circuit (IC) devices to a near ambient temperature level. This "desoak" thermal system addresses specific requirements of new IC panel (lead frame and strip) test handlers, which have very high peak processing capabilities and can operate stand-alone or in-line. Analyses are presented for estimating the heating and cooling loads, and the IC device temperature response. Temperature control methods are described that help minimize the system size. The hardware design is detailed along with experimental data that verifies the cooling capacity of the system.     

IC test structures for multilayer interconnect stress determination

A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results     

System-on-chip test scheduling with reconfigurable core wrappers

The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n); n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection tests and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound.     

Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology

The successful development of a new integrated circuit (IC) technology requires a significant effort in process evaluation. This is particularly true for the high-speed low-power planar GaAs digital IC technology, which involves a relatively new semiconductor material, new processing techniques, and pursues LSI complexity using very-fine-line lithography (1-µm dimensions). This paper contains a review of the strategy employed to monitor and evaluate each of the key process steps, and to evaluate the uniformity of device parameters. The principal process evaluation test structures are discussed along with measurement techniques, and examples of measurement results are given. Our emphasis on measurement automation to facilitate the collection of a large volume of data and their statistical analysis is reflected in the paper. Examples of wafer statistics are given.     

An hypothesis test technique for determining a difference insampled parts defective utilizing Fisher's exact test IC production

The result of sample testing during the production of integrated circuits is often a very small number of parts defective out of a sample which is itself very small compared to its population. The ability to determine a statistically significant difference when comparing the results of two such samples is critical in correctly evaluating the outcome of experiments. Fisher's exact test can be used in this situation because it is a method for testing the difference between two proportions of parts defective when the proportions are relatively small in comparison to the sample size. The results of the test are very accurate when the populations are at least ten times the sample size. The result of the test is independent of the order of the samples. However, because the test is one-sided, care must be taken to state the alternative hypothesis based upon the order of the magnitudes of the sample fractions defective     

Test response reuse-based SoC core test compression and test scheduling for test application time minimization

This paper presents a novel approach to system-on-a-chip (SoC) core test compression and test scheduling. Every test set is compressed through the test responses of its preceding core in preprocessing step by simulation. Consequently, under our method the test sets contain two parts: (1) the test sets that are compatible with the test responses of their individual preceding cores. This part can be removed from their original test sets, and (2) the test sets that none of the test vectors from them are compatible with the test responses of their individual preceding cores. On hardware implementation, only a couple of 2-1 MUXs are needed. The algorithms for reordering the sequences of core-under-tests and those of the test vectors for each corresponding core are outlined for optimal test compression results. It needs neither coder nor decoder, thus saving hardware overhead. Power-constrained SoC core test pipelining consumes less test application time. Hierarchical clustering-based SoC test scheduling can be implemented easily, and the hardware overhead is negligible. Experimental results on benchmark ISCAS 89 demonstrate that our method achieves significant improvement of test time and less ATE requirement over the previous methods, and it does not discount the fault coverage of each test set, moreover, the fault coverage for some test sets is improved instead.     

Integrity-based self-validation test scheduling

Intelligent sensors use functional self-testing to confirm measurement validity; this introduces the potential for false diagnosis and unnecessary corrective intervention. For a sensor in an integrity-monitoring context, it is desirable to select a test-interval to minimize the probability of faulty operation between discrete tests. The scheduling of discrete test intervals is examined as an optimization problem under a reliability-based cost-function. A convenient test-interval guideline, accounting for the operating context of the sensor, is derived for a simple case under limiting assumptions.     

Behavioral test generation modeling approach for mixed-signal IC verification

An application of behavioral modeling for mixed-signal test generation and applied results are presented. It is shown that test debugging can be provided in the verification test system before silicon by utilizing simulated behavioral mixed-signal models. Due to the behavioral modeling technique, the computational performance was enhanced to a level allowing efficient test development and debugging. Influence on efficiency in design methods is reported.     

数字集成电路功能测试仪的设计与实现

随着芯片速度和功能的不断提高,使芯片迅速投入量产变得困难。开发经济高效的测试仪器越来越重要。设计了一款基于E818管脚芯片最多128通道,10MHz测试速率的功能测试电路板,输出驱动达到±8V,输入比较电平达到±6V,每个通道可以动态地设置成输入、输出或者是三态。选用Alterastratix系列FPGA芯片,运用流水线技术,格雷编码来优化程序,完成对管脚芯片的一系列控制。采用阻抗匹配等手段解决信号完整信性问题。具有成本低廉,工作稳定,响应速度快的特点。     

Integrated test chips improve IC assembly

The use of test dies integrated with a semiconductor wafer to gauge environmental stresses effectively during the packaging and processing phases is discussed. These special-purpose assembly test chips (ATCs) are designed primarily for studying failures of the package-centered and composite types. These chips usually provide a way to stress the die, and they include transducers for monitoring the die's response to the stress. A variety of structures has been used to measure parameters associated with package-related failures. Corrosion detectors, moisture detectors, mechanical stress sensors, mobile ion sensors, thermal resistance measurement circuits, and multifunction test chips are examined     

肖钢:IC测试领域掘金人

2003年新年伊始,中国华大集成电路设计中心与安捷伦科技有限公司在京联合宣布,华大将引进安捷伦先进的93000 SOC测试系统,此举意味着华大IC测试部将成为国内北方地区第一家有能力提供SOC测试服务的机构,这无疑会对北京及周边地区正在崛起的IC设计公司提供有力的支持。而在华大,执掌     

一种数字电视传输误码率测试设备的设计与应用

介绍数字电视广播系统误码产生的原因及信道模型，描述一种数字电视传输误码率测试设备的帧格式，设备组成、工作原理，重点阐述了测试序列的产生和测试序列同步检测的设计。     

模拟IC自动测试系统的直流参数测试单元

模拟IC自动测试系统主要针对模拟IC的直流参数和交流参数进行测试,其中直流参数的测试是整个测试过程的重要部分。直流参数测试单元可以为芯片提供稳定的、精确的电压或电流,主要实现两种功能：一种是对待测芯片施加电压从而测量电流值,简称FVMI（加电压测电流）功能;另一种是对待测芯片施加电流从而测量电压值,简称FIMV（加电流测电压）功能。     

TCRS1A型IC卡指纹仪性能检测

在许多场合需要识别人身份的合法性，指纹识别就是其中的方法之一。指纹比对的正确率与其算法有着密切的关系。现讨论了TouchChip的TCRS1A指纹仪的使用性能，编制了一个将指纹存于IC卡中并进行比对的测试程序。通过运行，知其误识率很低，但传感器因表面人体油渍导致的指纹残留而提高了误识率。建议用户在使用前要充分考虑采用CMOS型指纹识别仪时指纹残留的影响。     

集成电路测试原理和向量生成方法分析

测试向量生成是集成电路测试的一个重要环节。在此从集成电路基本测试原理出发,介绍了一种ATE测试向量生成方法。通过建立器件模型和测试平台,在仿真验证后,按照ATE向量格式,直接生成ATE向量。以一种实际的双向总线驱动电路74ALVC164245为例,验证了此方法的可行性,并最终得到所需的向量文本。该方法具有较好的实用性,对进一步研究测试向量生成,也有一定的参考意义。