Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.     

Power-supply current diagnosis of VLSI circuits

This paper presents a technique based upon the power supply current signature (PSCS) which allows testing of mixed-signal systems, in situ. The PSCS contains important information concerning the operational status of the system; such information can be extracted using approaches based on statistical signal detection theory. The fault-detection performance of these techniques is superior to that achieved through autoregressive modeling of the PSCS. These methods are suitable for production testing of cost-sensitive devices and field testing of mission-critical systems     

Statistical timing and leakage power analysis of PD-SOI digital circuits

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

The mechanism of subthreshold leakage current in self-aligned gate GaAs MESFET's

The origin of the subthreshold leakage current in self-aligned gate GaAs MESFET's is investigated using temperature characterization, The leakage current is found to be comprised of two components, each dominant in a different temperature range. At temperatures below 0°C, space-charge-limited injection through the surface of the depleted channel dominates. At room temperature and above, the leakage current measured is the ohmic leakage through the bulk substrate. The space-charge-limited injection current is also found to be sensitive to the GaAs substrate quality.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

Current-mode techniques for high-speed VLSI circuits withapplication to current sense amplifier for CMOS SRAM's

The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access     

Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.     

Power distribution techniques for VLSI circuits

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.     

Minimization of MOSFET gate leakage current in buffer amplifier circuits

It is shown that the components of gate leakage current of a MOSFET used in a previously described unity gain buffer amplifier may be reduced to a minimum under static and dynamic conditions. Modified packaging and novel biasing techniques can minimize both extrinsic and intrinsic components of gate leakage current at the input to the amplifier.     

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400µm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, edge, striation, and gradient effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.     

UDSM subthreshold leakage model for NMOS transistor stacks

In this paper, a new, analytical model for subthreshold leakage estimation in the ultra deep submicron (UDSM) realm is proposed. Most previous attempts at subthreshold leakage estimation in transistor stacks are not tailored for the UDSM realm and are based on either a look up table approach, and/or assume that all the transistors in the stack have a fixed width. The analytical estimation model proposed in this paper is capable of estimating subthreshold leakage in UDSM NMOS transistor stacks with different transistor widths. The model achieves this by estimating the stack nodal voltages. In this paper, transistor stacks of two, three and four transistors are considered.Compared to SPICE simulations using PTM's BSIM4 models, our analytical model achieved an average error of 8.1% for the one, two, three and four transistor stacks for 65, 45 and 32 nm CMOS process technologies. The model also exhibits significant runtime savings when compared with SPICE.     

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.     

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.