High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunction bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. Our decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting f/sub T/ and f/sub max/ of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-performance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more.     

5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.     

A bipolar monolithic multigigabit/s decision circuit

A monolithic multigigabit/s decision circuit using a 0.5-/spl mu/m bipolar process technology called advanced super self-aligned technology (SST-1A) has been developed. A special decision circuit including a novel current switch based on a nonthreshold logic circuit and a cutoff prevention principle was designed and fabricated. An output voltage swing of 1 V across a 50-/spl Omega/ load, a fast transition time of 90 ps (10-90%) and 3.6 Gbit/s operation have been achieved. Power dissipation per chip is about 600 mW. This IC is applicable to very-high-speed optical fiber transmission system repeaters.     

High-bit-rate, high-input-sensitivity decision circuit using Sibipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-μm photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV_p-p. An extremely high input sensitivity of 15 mV_p-p and a wide phase margin of 260° at 10 Gb/s are achieved     

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μmGaAs MESFET's

This paper describes a 4O-Gbit/s decision integrated circuit (IC) fabricated with 0.12-μm gate length GaAs metal-semiconductor field-effect transistors (MESFET's). A superdynamic flip-flop circuit and a wide-band amplifier were applied in order to attain 40-Gbit/s operation. A conventional static decision IC was also fabricated for comparison. The dynamic decision IC operated up to 40 Gbit/s, which is twice as fast as the conventional static decision IC. Error-free 40-Gbit/s operation is the fastest among GaAs MESFET decision IC's     

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ atV_{CE} = 1V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.     

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.     

High-speed optical receiver with soft decision ISI cancellation

A receiver with soft decision intersymbol interference (ISI) cancellation (SDIC) is presented to deal with ISI in high-speed lightwave systems. The analytical and simulation results show that the transmission distance can be doubled with SDIC. In addition, the receiver with SDIC allows the ISI cancellation circuit to operate with a processing and propagation delay much longer than 1-b period. Therefore, it is very promising in very-high-bit-rate optical systems     

Symbolic simulation using decision diagrams

If decision diagrams (DDs) are used to represent the logical behaviour of a combinational logic circuit, then the representation is usually constructed by a traversal in topological order. At each gate the corresponding synthesis operation is carried out. This traversal process is called symbolic simulation. Obviously the sequence in which the operations are performed at each gate influences the number of nodes needed during computation. The authors consider different traversal strategies for OBDDs and OMDDs. The strategies are compared by means of experiments     

Smart optical receiver with automatic decision threshold settingand retiming phase alignment

The requirements for a smart optical receiver are discussed, and a design architecture suitable for introducing ICs based on automatic decision threshold setting and retiming phase alignment using digital/analog signal processing feedback is proposed. With the proposed architecture, the decision threshold level and the retiming clock phase of received data in the decision circuit are automatically adjusted to the optimum position. This obviates the need for decision threshold level and retiming clock phase adjustments in production testing, and it reduces the power penalty (receiver sensitivity degradation) on the received optical waveform variation. The power penalty caused by temperature and supply-voltage variations and aging in installation is also reduced. The performance of the proposed architecture is estimated; the power penalty as compared with the manual optimum adjustment is less than 0.4 dB, and the robustness to avalanche photodiode multiplication factor variations and crosstalk are improved     

Submicron silicon bipolar master-slave D-type flip-flop for use as 8.1 Gbit/s decision circuit and 11.2 Gbit/s demultiplexer

The authors have designed and implemented a submicron silicon bipolar master-slave D-type flip-flop integrated circuit which can be used either as a decision circuit or a demultiplexer, operating at data rates as high as 8.1 and 11.2 Gbit/s, respectively. The circuit was fabricated using a 0.6 mu m, nonpolysilicon emitter technology, occupying an area of 0.8 mm*0.9 mm, and dissipating 410 mW of power.<>     

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

A 45-Gb/s BiCMOS decision circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) circuits. In addition to the retiming flip-flop, the decision circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.     

AlGaAs/GaAs heterojunction bipolar transistor decision circuit

An AlGaAs/GaAs heterojunction bipolar transistor (HBT) decision circuit has been designed and characterised for optical communications, using 3.5 mu m emitter width transistors with cutoff frequency of 27 GHz. The maximum bitrate for a BER of 10/sup -9/ was 4.2 Gbit/s. At 2.0 Gbit/s, the clock phase margin was 240 degrees .<>     

50 Gbit/s low-jitter dynamic decision circuit using Cbc compensation and semi-feed forward techniques

A new low-jitter dynamic decision circuit is designed and fabricated using InP/InGaAs HBTs. Cbc compensation transistors and semi-feed forward loads are adopted to eliminate waveform distortion and residual double trace, respectively. A fabricated decision IC achieves error-free operation and wide eye opening for 50 Gbit/s 2/sup 31/-1 PRBS with 0.68 W power dissipation. Its RMS and peak-to-peak jitter of output data are 0.59 and 4.1 ps, respectively.     

The effect of decision delay in finite-length decision feedbackequalization

In this correspondence we derive the finite-length, minimum mean-squared error decision feedback equalizer (MMSE-DFE). We include decision delay as an explicit parameter. Our derivation yields an algebraic interpretation of the effect of decision delay on DFE performance (measured by mean-squared error). It also allows the fast computation of the MMSE-DFE for several different values of both decision delay and the number of feedback taps. Our approach is especially useful for short filter lengths, when the decision delay can significantly affect DFE performance     

Toward a decision informatics paradigm: a real-time, information-based approach to decision making

The focus of this paper is on decision making; more specifically, on what decision making requirements are needed in the future. We augur for a decision informatics paradigm; it is a real-time, information-based approach to decision making. The paradigm is supported by two sets of technologies (i.e., information and decision technologies) and underpinned by three disciplines (i.e., data fusion/analysis, decision modeling, and systems engineering). We begin by considering the context - and needs - for decision making as the economies of the world change and evolve, especially in regard to emerging services; then our proposed decision informatics paradigm is detailed and illustrated, together with an in-depth review of a critical, underpinning research area (dealing with real-time fusion and analysis of multiple nonhomogeneous data sources), followed by several concluding remarks.     

Social decision analysis

How can a diverse free society find decision mechanisms that are logical, efficient, and timely? This is a problem that has challenged man at least from the time of Plato's Republic. We see today factions of society arguing over alternatives rather than over values or probabilities. Adversary proceedings encourage people to advocate extremes rather than a careful balance of several considerations. Decision analysis, a logical procedure for balancing the many uncertain, complex, and dynamic factors that characterize a decision, offers promise of a new and valuable procedure for social decisions. The decision analyst creates an extrapersonal explicit model of the decision under consideration. Information on possible alternatives, uncertainties, relationships, or preferences can come from different groups and still be represented within the same decision model, with the implications for the decision apparent to all. One can imagine a society where decision making has become decentralized, where distinct bodies are responsible for creating social alternatives, assessing the probabilities of various outcomes for each alternative, and setting the preferences of society. Once the alternatives, information, and preferences were established, society would make the decision using only the principles of logic. Applications to automotive pollution, hurricane seeding, and nuclear safety demonstrate the approach.     

DSD (double soft decision) concatenated FEC scheme in mobilesatellite communication systems

In order to realize a higher-code-gain forward error correction scheme in mobile satellite communication systems, a novel concatenated coding scheme employing soft decision decoding for not only inner codes but also outer codes (double soft decision, or DSD, concatenated forward error correction scheme) is proposed. Soft-decision outer decoding can improve the bit error probability of inner decoded data. In this scheme, likelihood information from an inner Viterbi decoder is used in the decoding of outer codes. A technique using the path memory circuit status 1.0 ratio for likelihood information is proposed, and is shown to be the most reliable even though it requires the simplest hardware among the alternative methods. A computer simulation clarifies that the DSD scheme improves Pe performance to one-third of that of the conventional hard-decision outer decoding. Moreover, to reduce the interleaving delay time in fading channels or inner decoded data of concatenated codes, a parallel forward error correction scheme is proposed     

A novel high-speed latching operation flip-flop (HLO-FF) circuitand its application to a 19-Gb/s decision circuit using a 0.2-μm GaAsMESFET

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s     

Algorithm analysis and architecture design for rate distortion optimized mode decision in high definition AVS video encoder

There are abundant intra and inter prediction modes in the AVS video coding standard. Rate distortion optimized mode decision can fully utilize this flexibility to improve the spatio-temporal prediction efficiency and maximize the coding efficiency. However, the implementation complexity is dramatically high due to huge throughput burden. Hardware oriented mode decision algorithm is tailored for VLSI implementation in this work for high definition video coding. Mode preselection is employed to alleviate the dramatic throughout burden. Also, intelligent pipeline scheduling mechanism is proposed to break the intrinsic data dependency in intra prediction, which is directly related with mode decision. The proposed simplified algorithm is well-suited for hardware implementation with small performance penalty. Finally, the VLSI architecture is proposed with good trade off between circuit consumption and rate distortion performance.