不同退火温度下Mo/4H-SiC肖特基接触界面特性分析

为研究退火温度对肖特基接触界面特性的影响,在不同温度下测试了不同退火温度处理的Mo/4H-SiC肖特基接触的I-V及C-V特性.根据金属-绝缘层-半导体(MIS)结构二极管模型理论,认为在金属与半导体间存在薄介质层,通过估算介质层电容值,得到了肖特基接触界面态密度(N88)的能级分布情况,N8s约为1012 eV-1·cm-2量级.退火温度升高,N8s的能级分布靠近导带底;测试温度升高,Ns8增加且其能级分布远离导带底.利用X射线光电子能谱(XPS)分析表征肖特基接触界面态化学组分,分析结果证实接触界面存在SiO.SiO组分随退火温度的升高而减少,在退火温度为500℃及以上时检测到Mo-C成分,说明Mo与4H-SiC发生反应.     

SiO2/SiC界面陷阱电荷近似计算的局限

从理论上分析了近似计算所引起的SiC基MOSFET两个重要参数阈值电压和沟道电流的误差.结果显示,在很多情况下近似计算都会带来很大的误差(＞5%),尤其对于沟道电流,在大部分情况下误差很大,只是在少数条件下误差较小(＜5%).因此,近似计算SiO2/SiC界面陷阱电荷不尽合理,应利用电子在界面态上的分布函数进行准确计算.     

CuPc/SiO2表面界面的电子状态研究

利用热生长工艺和热蒸发方法分别获得CuPc和SiO2薄膜层,通过原子力显微镜和X射线光电子能谱对其表面界面电子状态进行了研究,并采用高斯拟合方法对各谱进行了详细分析.结果表明,在氧原子的作用下,N1s,C1s,O1s 和Cu2p都经受了一定的化学位移,从而使得各原子间的相互作用强度有所改变,这是导致OFET性能劣化的重要原因之一.对OFET而言,采用溅射工艺制备的SiO2层应比热氧化生长的SiO2层更合适.     

磁控溅射制备磁性多层膜中SiO2/Ta界面的研究

磁性多层膜常用磁控溅射的方法制备，并且以金属Ta做为缓冲层。本研究利用这种方法在单晶硅基片上沉积了Ta/NiFe/Ta薄膜。采用X射线光电子能谱（XPS）对该薄膜进行了深度剖析，并且对获得的Ta4f和Si2p的高分辩率XPS谱进行计算机谱图拟合分析。结果表明：磁控溅射这种高能量制膜技术导致了在SiO2/Ta界面处发生了化学反应：15SiO2 37Ta=6Ta2O5 5Ta5Si3，该反应使得界面有“互混层”存在，从而导致诱发NiFe膜（111）织构所需的Ta缓冲层实际厚度的增加。从本研究还可以看出XPS是表征磁性薄膜界面化学状态的一种有利工具。     

CuPc/SiO2的表面界面电子状态研究

本文通过热生长工艺和热蒸发方法分别获得CuPc和SiO2薄膜层，通过原子力显微镜和x射线光电子能谱对其表面界面电子状态进行了研究，并采用高斯拟合的方法对各谱进行了详细的分析。研究结果表明，在氧原子的作用下，N1s, C1s, O1s 和Cu2p都经受了一定的化学位移，从而使得各原子间的相互作用强度有所改变，这可能是导致OFET性能劣化的重要原因之一。结果也表明，对OFET而言，采用溅射工艺制备的SiO2层应比热氧化生长的SiO2层的OFET要更合适。     

SiO_2/SiC界面的Wet-ROA改性机理研究

高温热氧化法在4H-SiC(0001)晶面上生成SiO2氧化膜,采用湿氧二次氧化(wet-ROA)工艺对样品进行处理,通过测量SiCMOS结构界面电学特性,发现wet-ROA工艺有助于降低界面态密度,改善SiO2/SiC界面电学特性。采用变角X射线光电子能谱(ADXPS)技术对SiO2/SiC界面过渡区进行分析,通过过渡区厚度计算和过渡区成分含量比较,发现湿氧二次氧化工艺可减小过渡区氧化膜厚度,降低过渡区成分含量,进而揭示了降低SiO2/SiC界面态密度,改善界面电学特性的微观机理。     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

SiO2/Ta界面反应及其对铜扩散的影响

利用磁控溅射方法在表面有SiO2层的Si基片上溅射Ta/NiFe薄膜,采用X射线光电子能谱(XPS)研究了SiO2/Ta界面以及Ta5Si3标准样品,并进行计算机谱图拟合分析.实验结果表明在制备态下在SiO2/Ta界面处发生了热力学上有利的化学反应:37Ta+15SiO2=5Ta5Si3+6Ta2O5,界面处形成更稳定的化合物新相Ta5Si3、Ta2O5.在采用Ta作阻挡层的ULSI铜互连结构中这些反应产物可能有利于对Cu扩散的阻挡.     

SiO2/Ta界面反应及其对铜扩散的影响

利用磁控溅射方法在表面有SiO2层的Si基片上溅射Ta/NiFe薄膜,采用X射线光电子能谱(XPS)研究了SiO2/Ta界面以及Ta5Si3标准样品,并进行计算机谱图拟合分析.实验结果表明在制备态下在SiO2/Ta界面处发生了热力学上有利的化学反应:37Ta+15SiO2=5Ta5Si3+6Ta2O5,界面处形成更稳定的化合物新相Ta5Si3、Ta2O5.在采用Ta作阻挡层的ULSI铜互连结构中这些反应产物可能有利于对Cu扩散的阻挡.     

ZrN扩散阻挡层与SiCON低k介质界面特性XPS研究

对ZrN扩散阻挡层与SiCON低k介质(k=2.35)的界面特性进行了XPS分析。实验结果表明,刚淀积的样品中ZrN与SiCON薄膜之间有一定程度的相互扩散并形成界面区。在界面区内Zr与SiCON薄膜中O及N元素相互作用成键,表明ZrN/SiCON界面有良好的黏附性能。400℃退火后,除受表面氧化作用干扰的O和N元素外,未观察到界面中其他元素Zr,Si和C有新的扩散,说明界面稳定性很好。     

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

In this work we investigate the effects of NO annealing and forming gas (FG) an-nealing on the electrical properties of SiO2/SiC interface by low-temperature con-ductance measurements. With nitrogen passivation, the density of interface states (DIT) is significantly reduced in the entire energy range, and the shift of flatband voltage, ΔVFB, is effectively suppressed to less than 0.4 V. However, very fast states are ob-served after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and ΔVFB are further re-duced. The values of the DIT decrease to less than 1011 cm-2eV-1 for the energy range of EC-ET≥0.4 eV. It is suggested that the fast states in shallow energy levels origi-nated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the re-sidual Si and C dangling bonds corresponding to traps at deep energy levels and im-prove the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high perfor-mance SiC MOSFETs.     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

一氧化氮退火对高温氧化SiC/SiO2界面特性的影响研究

本文研究了高温（1300℃）氧化并在一氧化氮（NO）气体中进行氧化后退火方法对4H-SiC 金属-氧化物-半导体（MOS）电容的SiC/SiO2界面特性的影响,主要通过SiC MOS的电容-电压(C-V)特性详细讨论了NO退火时间和温度与SiO2/SiC界面特性的相互关系. 结果表明在NO气体中进行氧化后退火可明显降低界面态密度,并且界面态密度随着温度和时间的增加会进一步降低。 同时,与常规1200℃及以下氧化温度相比,1300℃下热生长的氧化层具有更低的界面态密度且显著缩短了氧化时间,节约了生产成本。     

Effect of epilayer characteristics and processing conditions on the thermally oxidized SiO2/SiC interface

The optimization of the SiO₂/SiC interface is critical for the development of SiC MOS devices. We investigate the effects of several variables spanning both epilayer attributes and processing conditions relative to our control oxidation process. Varying the shallow vicinal angle of the wafer does not affect the interface. There is a definite degradation of the interface as the epilayer doping density is increased. Sacrificial oxidation appears to reduce the number of border traps in the final oxide. Fluorine annealing has no effect on the interface quality. A low temperature (950°C) re-oxidation, which follows a bulk oxide growth at 1150°C, reduces D _it to the mid-10¹⁰ cm⁻²eV⁻¹ range near midgap and Q_f to a reacord low 5×10¹¹ cm⁻².     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface

The response time of deep-lying interface states in silicon carbide metal-oxide semiconductor (MOS) capacitors may be thousands of years at room temperature. To accurately measure interface state density beyond about 0.6 eV from the band edge, it is necessary either to raise the temperature well above 300K so that all states can follow changes in DC bias, or to utilize photoexcitation to modulate the interface state population at room temperature. In this paper, we use the hilo capacitance-voltage technique and the ac conductance technique at elevated temperatures to characterize the MOS interface of p-type 6H-SiC. We report on the effect of surface cleaning and push/pull rates, and give the first detailed comparison of the effect of aluminum vs boron as the p-type dopant on the MOS interface. Oxides grown on 6H-SiC at 1150°C in wet O₂ followed by a 30 min insitu argon anneal have fixed charge densities as low as 9 x 10¹¹ cm^-2 and interface state densities as low as 1.5 x 10¹¹ cm^-2 eV^-1.     

Laser-induced self-organization of nano-wires on SiO2/Si interface

Original observation of new graded band gap structures formed on the surface of elementary Si semiconductor at studying the optical properties of Si nano-hills formed at the SiO₂/Si interface by pulsed Nd:YAG laser irradiation is reported. The self-organized nano-hills on Si surface are characterized by a strong photoluminescence in the visible range of spectrum with a shoulder extended to the long-wave part of the spectrum. The feature is explained by the quantum confinement effect in nano-hills-nano-wires of gradually changing diameter.     

Effect of H2O evolving from TEOS based SiO2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H₂O) molecules evolving from silicon dioxide (SiO₂) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H₂O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H₂O molecules lower threshold voltage (V_t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V_t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.     

基于SiO2溶胶的稳定性的Cu/SiO2催化体系在化学机械抛光中的应用研究

There is a lot ofhydroxyl on the surface ofnano SiO2 sol used as an abrasive in the chemical mechanical planarization （CMP） process, and the chemical reaction activity of the hydroxyl is very strong due to the nano effect. In addition to providing a mechanical polishing effect, SiO2 sol is also directly involved in the chemical reaction. The stability of SiO2 sol was characterized through particle size distribution, zeta potential, viscosity, surface charge and other parameters in order to ensure that the chemical reaction rate in the CMP process, and the surface state of the copper film after CMP was not affected by the SiO2 sol. Polarization curves and corrosion potential of different concentrations of SiO2 sol showed that trace SiO2 sol can effectively weaken the passivation film thickness. In other words, SiO2 sol accelerated the decomposition rate of passive film. It was confirmed that the SiO2 sol as reactant had been involved in the CMP process of copper film as reactant by the effect of trace SiO2 sol on the removal rate of copper film in the CMP process under different conditions. In the CMP process, a small amount of SiO2 sol can drastically alter the chemical reaction rate of the copper film, therefore, the possibility that Cu/SiO2 as a catalytic system catalytically accelerated the chemical reaction in the CMP process was proposed. According to the van＇t Hoff isotherm formula and the characteristics of a catalyst which only changes the chemical reaction rate without changing the total reaction standard Gibbs free energy, factors affecting the Cu/SiO2 catalytic reaction were derived from the decomposition rate of Cu （OH）2 and the pH value of the system, and then it was concluded that the CuSiO3 as intermediates of Cu/SiO2 catalytic reaction accelerated the chemical reaction rate in the CMP process. It was confirmed that the Cu/SiO2 catalytic system generated the intermediate of the catalytic reaction （CuSiO3） in the CMP process through the removal rate of copper film, infrared spectrum and AFM diagrams in different pH conditions. FinalLy it is concluded that the SiO2 sol used in the experiment possesses stable performance; in the CMP process it is directly involved in the chemical reaction by creating the intermediate of the catalytic reaction （CuSiO3） whose yield is proportional to the pH value, which accelerates the removal of copper film.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.