A simple model of the threshold voltage of short and narrow channel MOSFETs

Simple but reasonably accurate equations are proposed which describe the behavior of threshold voltage for short and narrow-channel MOSFETs, for low drain-source voltages.

It will be shown that good agreement is obtained between the model, experiment and two dimensional calculations, for channel lengths and widths as small as 1 2 μm. Moreover, by careful analysis of the model results, some new properties of the threshold voltage of small size devices can be derived.     

Analytical threshold voltage model for short channel double-gateSOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V_th, we derived a model for V_th of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, ΔV_th, and subthreshold swing (S-swing) degradation with decreasing gate length L _G, and showed that we can design a 0.05-μm-L_G device with ΔV_th of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

Analytical model of body factor in short channel bulk MOSFETs for low voltage applications

An analytical model to study the degradation of body factor (γ) and subthreshold factor (S) of short channel bulk MOSFETs have been developed and the expression for body factor of short channel devices is derived. Modified relation between S and γ factors has also been obtained and a correction factor γ_s is found which maintained the conventional relation in spite of the degradation of these two parameters in short channel devices. Results obtained are found in good approximation with 2D simulated data.     

异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*

本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型．并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究．该模型中考虑以下参数：金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分．结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL．同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率．此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高．数值模拟器ISE验证了该模型的正确性．     

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain ...     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

A quasi-3D analytical threshold voltage model of small geometry MOSFETs

Numerical 2D and 3D models of MOSFETs, which have been developed so far, are accurate but take enormous computer time and memory for their implementation. It restricts their use only to the design and development of submicron devices. A computationally faster, analytical quasi-3D model for the threshold voltage of small geometry MOSFETs, which should be useful for VLSI circuit simulation, has been presented in this paper. The model is based on a rigorous 2D analytical model. An equivalence between the analytical 2D model and the Yau's charge sharing model has been established, and the same has been utilized to incorporate the narrow width effect. The important features of the present work are: (1) realistic channel implantation profiles for nMOSFETs have been used in developing the 2D model; (ii) the effect of birds' beaks on the lateral confinement of charges in the channels of oxide isolated MOSFETs has been considered in a simple manner; and (iii) the fringing of electric field near the edges of channels (widths) has also been considered empirically. The simulated values of the threshold voltages exhibiting 2D and 3D effects compare well with those obtained using a numerical 3D simulator (MICROMOS) and with available experimental data. The model is also capable of predicting the inverse narrow width effect observed in MOSFETs with fully recessed field oxide.     

A new threshold voltage model for deep-submicron MOSFETs with nonuniform substrate dopings

A simple but accurate threshold voltage model for deep-submicron MOSFETs with nonuniform dopings is described in this paper. In this model, a simplified quasi-delta substrate doping profile is used to approximate the nonuniformity. We apply a hyperbola function to avoid the discontinuous problem at the boundary between different doping regions. By adjusting the parameter δ, the actual gradual doping profile can be obtained. A substrate-bias dependent model of short channel effect is also introduced which describes the reduction of substrate-bias effect in deep-submicron devices. The model developed is in good agreement with two-dimensional numerical simulation.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator.     

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements     

A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

An accurate analytical threshold voltage model is presented for fully-depleted SOI n-channel MOSFETs having a metal-insulator-semiconductor-insulator-metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Since the inversion charge is proportional to the drain current at low bias, the model is self-consistent with the measurement scheme when the threshold voltage is measured as the gate voltage at which the variation of the transconductance at low drain bias is maximum. Numerical simulations show good agreement with the model with less than 3% error.     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

A new boron implantation model suitable for analytical modeling of threshold voltage of MOSFETs

The boron implantation profile in silicon is usually simulated by the Pearson-IV distribution function with some modifications, as in SUPREM. But this function is complex from the point of view of analytical modeling. New functions which fit very well with SUPREM simulated implantation profiles for boron in silicon have been proposed in this paper. These functions, being analytically integrable, allow us to formulate accurate analytical models of threshold voltages of MOSFETs with implanted channels. In this paper models for the threshold voltages of both long channel and short channel NMOSFETs have been presented. For the long channel case, the results agree very well with those obtained from numerical computations with considerable saving of computation time. The results of the short channel model also show good agreement with available experimental data.     

Analytical threshold voltage model for short channeln+-p+ double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n⁺-p⁺ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift ΔVth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 μm L_G device of which threshold voltage is 0.2 V, ΔVth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI     

A comparison of simple and numerical two-dimensional models for the threshold voltage of short channel MOSTs

The threshold voltage for short channel MOSTs has been derived by two-dimensional numerical computation. The results can be expressed in normalised form with the reduced threshold voltage, V_T ? V_FB ? 2φ, given as a fraction of the reduced long-channel threshold voltage, V_T∞ ? V_FB ? 2φ, where V_FB and φ are the flat-band and bulk Fermi potentials respectively. An extremely good fit to the theoretical predictions is then given by

$\text{V}{}_{\mathrm{T}}\text{?V}{}_{\mathrm{FB}}\text{?2φ}\text{V}{}_{\mathrm{T\infty }}\text{?V}{}_{\mathrm{FB}}\text{?2φ}\text{=1?}\text{aW}{}_{\mathrm{sr}}\text{L}{}^{\mathrm{b}}$

where

$\text{a?0.94?0.17}\text{W}{}_{\mathrm{s}}\text{rj}{}^{\mathrm{<mtext>1</mtext><mtext>2</mtext>}}$

$\text{b?0.90?0.66}\text{log}{}_{10}\text{W}{}_{\mathrm{s}}\text{r}{}_{\mathrm{j}}\text{+0.37}\text{X}{}_{\mathrm{ox}}\text{W}{}_{\mathrm{s}}$

where the junction depth, r_j, and oxide thickness, x_ox, are expressed as fractions of the source depletion layer thickness, W_s, and where the channel length, L, is given as a fraction of the one-dimensional theoretical spread, W_sr, of a depletion region around a cylindrical step-junction.This empirical expression is valid over a wide range of normalised device geometries (0.4 < L/W_sr < 40, 0.1 < r_j/W_s < 10, 0.01 < x_ox/W_s < 0.2) and, except for very shallow junctions (r_j/W_s ? 1), differs only slightly from the simple model proposed by Yau. A comparison of the theory with experimental results shows good agreement for MOSTs fabricated with channel lengths between 2 and 5 μm using conventional photolithography.