共振隧穿电路中翻转-传输代数系统的建立

在传统数字电路天关一信号理论的基础上.提出了一个全新的基于共振隧穿RT(Resonant Tunneling)电路的翻转-传输理论,建立了适用于共振隧穿电路的翻转-传输代数系统,确定了两种联结运算,并用共振隧穿器件实现了该两种联结运算的基本电路结构.为设计共振隧穿电路特别是基本逻辑电路提供了一个全新的理论基础和系统的设计方法.     

基于RT器件的三值与非门、或非门电路设计

共振隧穿(resonant tunnel,RT)器件本身所具有的微分负阻(negative differential resistance,NDR)特性使其成为天然的多值器件.文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性.该设计思想可推广到更高值的多值电路设计中.     

基于RT器件的三值与非门、或非门电路设计

共振隧穿（resonant tunnel,RT）器件本身所具有的微分负阻（negative differential resistance,NDR）特性使其成为天然的多值器件，文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性，该设计思想可推广到更高值的多值电路设计中。     

一种利用共振隧穿二极管简化电路的分频器设计

提出了一种基于共振隧穿二级管的新型边沿触发D触发器并将之用于构成二进制分频器.详细讨论了设计过程,用SPICE验证了电路的功能,并和已有的设计进行了比较.由于利用了共振隧穿二极管高度的非线性,同CMOS分频器相比,电路中元件的数量可以减少一半.     

一种利用共振隧穿二极管简化电路的分频器设计

提出了一种基于共振隧穿二级管的新型边沿触发D触发器并将之用于构成二进制分频器.详细讨论了设计过程,用SPICE验证了电路的功能,并和已有的设计进行了比较.由于利用了共振隧穿二极管高度的非线性,同CMOS分频器相比,电路中元件的数量可以减少一半.     

小偏压下阱中阱结构的量子隧穿特性及其实现

共振隧穿是电子的隧穿概率在某一个能量值附近以尖锐的峰值形式出现的隧穿,是目前为止最有希望应用到实际电路和系统的量子器件之一,其特点是器件的响应速度非常快。本文用传递矩阵的方法分别计算了在外加偏压下,对称双势垒、三势垒应变量子阱结构的透射系数与入射电子能量和隧穿电流与偏置电压的关系,模拟了应变多量子阱结构的隧穿系数和I-V特性曲线。计算得到隧穿电流峰值位置与实验测试值符合得很好,对于设计共振隧穿二极管并为进一步实验提供理论指导具有重要的意义。     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

共振隧穿器件应用电路概述——共振隧穿器件讲座(2)

在“共振隧穿器件概述”的基础上,对共振隧穿器件应用电路作了全面概括的介绍。首先对共振隧穿器件应用电路的特点、分类和发展趋势作了简述;进一步对由RTDH/EMT构成的单-双稳转换逻辑单元(MOBILE)和以它为基础构成的RTD应用电路,包括柔性逻辑、静态随机存储(SRAM)、神经元、静态分频器等电路的结构、工作原理和逻辑功能等进行了介绍。关于RTD/HEMT构成的更为复杂的电路,如多值逻辑、AD转换器以及RTD光电集成电路等将在本讲座最后部分进行讲解。     

多峰I—V特性的共振隧穿量子器件

讨论了电子对双势垒共振隧穿的现象和特性,较为详细地论述了近年来发展起来的具有多峰I—V特性的共振隧穿量子器件的原理、结构和电路应用,最后展望了这类器件的发展前景。     

Ultrahigh-speed heterojunction bipolar transistormultiplexer/demultiplexer ICs

High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively     

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297–298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.     

Design approach using tunnel diodes for lowering power in differential comparators

Adding two clocked tunnel diode pairs to the output ports of a differential amplifier enables high-speed current-mode switching at a lower tail current than in a transistor-only differential pair. The addition of the tunnel diodes also lowers the output open-circuit time constant of the differential pair leading to faster switching speed. As a design example, a return-to-zero D flip-flop is simulated for use as the decision circuit in a single-bit oversampling digital-to-analog converter. Indium phosphide-based heterojunction bipolar transistors and resonant tunneling diodes are used in the model simulation; both conventional and tunnel-diode-augmented circuits are compared. Power dissipation of 3.5 mW/latch at 100-GHz clock frequency with 60-dBc spur-free dynamic range (SFDR) is obtained in the tunnel diode/transistor flip-flop. In comparison with the transistor-only approach, power is reduced by approximately 1.6/spl times/ at the same speed and SFDR.     

Digital circuit applications of resonant tunneling devices

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates     

硅基隧穿二极管

隧穿二极管是一种很有前途的基于带隙工程的异质结构量子器件,其电流电压(I-V)曲线中所呈现的微分负阻特性能够用于开发多种不同的电路功能。在最近的研究中,空穴型双势垒单势阱共振隧穿二极管得到了实现,为Si1-xGex/Si异质结隧穿二极管器件的改进和电路应用打下了良好的基础。     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

Design of sequential circuits by quantum-dot cellular automata

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.