可自适应变频嵌入式微处理器核的设计

变频技术是一种非常实用的低功耗设计技术．本文设计了与MIPS32—4Kec指令兼容的嵌入式微处理器核SRISC—I，并内嵌锁相环（PLL）作为时钟发生电路，该微处理器核在软件控制下可自适应地改变工作频率．除正常的工作模式外，SRISC—I还支持空闲、体眠模式，可停止整个系统时钟及PLL的运行，有效地降低了功耗．仿真结果表明，在0．1SumCMOS工艺下，SRISCI最高频率达到250MHz，在PLL的控制下其工作频率可以以10MHz的步长改变．同时，给出了SRISC—I在不同频率下运行Dhrystone2．1程序的功耗，250MHz时为82．466m Watt，而在体眠模式下仅为28uWatt．     

0.001 3 mm2自动频率校正算法电路的设计及应用

在高速串行接口PCIE2.0的设计中,为了保证数据传输的正确性,数据串行传输的工作时钟需要在很短的时间内完成锁定。为了减小锁相环的锁定时间,提高时钟稳定性,在传统的顺序搜索自动频率校正算法电路的基础上,提出了一种新的二进制搜索算法校正电路,并且应用于5 GHz的锁相环中,最大校正时间为22.5 μs。锁相环在SMIC 55 nm CMOS工艺下流片,SS工艺角下,AFC电路的面积为0.001 3 mm2。经测试,锁相环能够快速锁定,性能良好。     

一种用于高速PLL的CMOS电荷泵电路的设计

通过对电荷泵电路中存在的电荷注入、时钟馈通、电荷共享等现象的分析,设计了一个新型的高速电荷泵锁相环.电荷泵的设计是根据Mentor Graphics的eldo平台仿真CMOS0.35um技术.工艺,.仿真采用3.3V电源电压供电,功耗为0.47mW.仿真结果表明,该电荷泵电路可以很好地满足高速锁相环电路的要求.     

FPGA时钟分配网络设计技术

本文阐述了用于FPGA的可优化时钟分配网络功耗与面积的时钟布线结构模型.并在时钟分配网络中引入数字延迟锁相环减少时钟偏差,探讨了FPGA时钟网络中锁相环的实现方案.     

光通信系统2．5Gbps双环结构CDR电路设计

本文论述了基于锁相环（PLL）技术的2．5Gbps数字时钟恢复（cDR）电路的实现,采用LC谐振结构实现了优异的抖动性能指标。测试结果表明,本电路可以用作光通信系统STM-16光口侧下行数据的中继和再生。     

一种低抖动快锁定的时钟数据恢复电路设计

采用TSMC 0.13μm CMOS工艺,设计了一种基于延迟锁相环(DLL)与锁相环(PLL)混合技术的时钟数据恢复(CDR)电路。它结合延迟锁相环电路追踪速度快和锁相环电路抖动抑制能力强的特点,与通常基于二阶锁相环结构的电路相比,在输出抖动相同的情况下,具有更快的锁定时间。仿真结果表明该电路可以成功恢复出480 MHz伪随机数据,数据峰峰值抖动约为39 ps,即相对抖动约为0.02 UI,锁定时间约为793 ns,较二阶锁相环结构的电路提升了32%。芯片核心电路面积为0.15 mm2,1.2 V电源供电下消耗功耗6.9 m W。     

高性能微处理器微体系结构级功耗模型及分析

基于Itanium2微处理器体系结构提出单时钟和多时钟域两种基准模型；对处理器的电路级特性进行微体系结构级抽象，建立了参数化的峰值功耗估算模型；提出事件调度算法，实现了多时钟域处理器系统的行为级模拟；以IMPACT工具集作为模拟引擎实现了处理器的动态功耗模拟模型．与其它同类模型Wattch相比，该模型能够支持多时钟系统的模拟，峰值功耗估算精度高了约3％，而模拟速度提高了42％．通过实验说明了多时钟域的功耗特性，在一种多电压和频率环境下，多时钟域处理器的功耗和能量分别降低了21％和38％．该模型可以很好地应用到体系结构级低功耗研究设计．     

一个改进型CMOS电荷泵锁相环的设计

本文针对传统电荷泵电路的非理想效应,对CMOS锁相环中的电荷泵电路进行了改进,设计了一种采用电流控制技术的新型pump-up电荷泵.采用标准chartered 0.35um/3.3V模型,通过Cadence Spectre仿真,仿真结果显示,该锁相环有效地抑制了电荷共享和电流失配非理想特性的影响,消除了锁相环输出抖动,可稳定输出13.56MHz时钟信号,稳定时间小于11.2us,功耗小于 18mW.     

一种用于高速锁相环的零死区鉴频鉴相器

本文探讨鉴频鉴相器(PFD)设计中死区的产生原因和消除方法。设计了一种用于高速锁相环的零死区PFD。这种PFD采用无反馈回路结构,在保证死区为零的前提下,兼顾功耗和速度性能。尤其适用于基于锁相环的高速时钟和数据恢复电路(CDR)、高速频率合成器等对速度和抖动性能有很高要求的电路。     

时钟芯片的低功耗设计

在时钟芯片设计的各个层次上深入探讨了影响时钟芯片功耗的主要因素,确定了电路功耗主要来源与振荡电路和分频电路。在电路实现过程中,通过采用不同工作电压和对主要功耗电路的结构和参数进行优化设计等多种手段来控制功耗。通过1.2滋m工艺流片验证,在工作电压为5V时,芯片工作电流为0.17mA,实现了低功耗时钟芯片的设计。     

Design and simulation of a standing wave oscillator based PLL

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.     

A novel clock generation algorithm for system-on-chip based on least common multiple

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.     

一种全数字锁相环的设计与应用

介绍一种采用FPGA设计实现的ADPLL的结构及特点,并用该锁相环产生SDH设备的外同步时钟。由于该锁相环的负反馈时钟采用了初始受控分频设计、并采用了合理的环路滤波算法,该ADPLL同传统的数字锁相环(DPLL)一样,在参考源切换过程中输出时钟平滑稳定;同时也和传统的模拟锁相环(APLL)一样,在锁定状态下有稳态相差。对输出时钟的测试表明,该ADPLL产生的SDH外同步输出时钟满足系统的应用要求。     

Measuring jitter and phase error in microprocessor phase-lockedloops

The use of phase-locked loops (PLLs) for clock generation in modern microprocessors has been proliferating in recent years. This is because PLLs have the advantages of allowing multiplication of the reference clock frequency and allowing phase alignment between chips. The PLL locks to a reference clock but can generate output clocks that are a multiple of the reference. It is argued that excessive “jitter”, caused primarily by power supply noise, can detract from the advantages of phase-locked loops. Moreover, in a multichip system, the accumulated phase error must be measured-not just the jitter     

Wide range-low jitter PLL design for serializer

The paper presents the wide range phase-locked loop design for serializer. Serializer converts the 16 bit parallel data into serial, thus 16 times fast clock is required to synchronize the parallel data and serial data. PLL generates 16× serial clock from the parallel clock by frequency multiplication. PLL is simulated with 0.18 µm CMOS process. Major challenge of PLL design is to achieve large dynamic range. The PLL design for large dynamic range suffers from a high jitter at lower frequency and linearity issues. Advance CSVCO has been simulated with source degeneration technique and achieve wide linear range from 14 MHz to 1.05 GHz with 99.2 % linearity. The PVT Corners simulation shows 16 MHz to 1.04 GHz output range. Average power dissipation of the proposed PLL design is 2.7 mW. Worst case Peak to peak period jitter is 13.4 ps and rms jitter is 2.6 ps for 800 MHz output frequency.

     

无晶振快速锁定高精度锁相环设计

提出了一种无晶振锁相环结构,可快速锁定所需频率,并对模拟和数字模块分别进行了验证。模拟模块原理与经典结构相似,数字跟踪分频器模块利用初始时PLL不精确时钟搜索系统中的信号,根据搜索到的基准时钟调整PLL的输出,只需一个主机基准信号就可精确锁定所需的时钟频率。     

基于时钟同步技术在数据采集系统中的应用

介绍了一种系统时钟信号同步设计。为了提高系统时钟同步技术以及系统的可靠性,以现场可编程阵列（FPGA）代替传统的处理器为控制核心,采用锁相环（PLL）和Verilog硬件描述语言进行设计,达到复位实现时钟同步目的。实践证明,该设计运行稳定,可靠性强,适合在高速工作时钟下工作。     

用于高精度图像传感器的锁相环

为了提高图像传感器的探测精度,给像素中的传输管提供高精度时钟信号,设计了一款可编程式电荷泵锁相环(Phase-Locked Loop,PLL)模块。该模块使用分频器以输出可调控频率的时钟,增加了复用性;在电荷泵中加入单位增益放大器以消除毛刺,增大了锁相环精度;同时给出了针对整个模块的相位噪声分析。仿真结果表明,当输出200 MHz时钟时,信号的时钟抖动为28 ps,电路工作在1.5 V电压下的功耗<2 mW。该模块已用于一款高精度图像传感器中,在0.11μm CMOS工艺下进行了流片,测试结果表明其可以实现50 MHz到200 MHz的高精度时钟输出,满足了芯片对于时钟的需求。     

Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI

Nine D-type Flip-Flop (DFF) architectures were implemented in 28 nm FDSOI at a target, subthreshold, supply voltage of 200 mV. The goal was to identify promising DFFs for ultra low power applications. The single-transistor pass gate DFF, the PowerPC 603 DFF and the C²MOS DFF are considered to be the overall best candidates of the nine. The pass gate DFF had the lowest energy consumption per cycle for frequencies lower than 500 kHz and for supply voltages below 400 mV. It was implemented with the smallest physical footprint and it proved to be functional down to the lowest operating voltage of 65 mV in the typical process corner. During Monte Carlo (MC) process and mismatch simulations it was also found that the pass gate DFF is least prone to variations in both minimal setup- and minimal hold-time. Race conditions, during mismatch variations, occurred for the flip-flop that is constructed from NAND and inverter based multiplexers. The pass gate DFF is outperformed slightly when it comes to D-Q-based power-delay product and more significantly when it comes to the maximum clock frequency. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop, these also had the lowest D-Q-based power-delay of 26% and 30% respectively of that of the worst-case S²CFF power-delay product.