SiGe/Si异质结缺陷的光致发光研究

本文用光致发光(PL)光谱对Si0.87Ge0.13/Si异质结的缺陷进行了研究。对PL光谱中与SiGe外延层应变驰豫产生的失配位错相关的D-Band进行了分析,发现应变驰豫同时在SiGe层和Si衬底中诱生了位错。由于在PL光谱中观察到了D1而没有观察到D2,因此D1,D2很可能并不对应于相同的位错。通过进一步的分析,我们推测引起SiGe/Si异质结的PL光谱中D-Band的位错的微观结构很可能和Si-Si相关。     

SiGe电荷注入晶体管的直流特性模型

为了能直观地体现SiGe/Si电荷注入晶体管的收集极电流与漏源电压的关系，利用输入端SiGe/Si量子阱中二维空穴气的隧道模型，建立起此类器件的输入输出数学模型，并利用MATLAB软件对所建模型进行了模拟，结果显示在漏源电压约为1.5 V时，漏电流出现较强的负微分电阻效应，与文献报道结果符合. 关键词： SiGe/Si异质结 电荷注入晶体管 二维空穴气 隧道效应     

异质多晶SiGe栅应变Si NMOSFET物理模型研究

结合了“栅极工程”和“应变工程”二者的优点, 异质多晶SiGe栅应变Si MOSFET, 通过沿沟道方向使用不同功函数的多晶SiGe材料, 在应变的基础上进一步提高了MOSFET的性能. 本文结合其结构模型, 以应变Si NMOSFET为例, 建立了强反型时的准二维表面势模型, 并进一步获得了其阈值电压模型以及沟道电流的物理模型. 应用MATLAB对该器件模型进行了分析, 讨论了异质多晶SiGe栅功函数及栅长度、衬底SiGe中Ge组分等参数对器件阈值电压、沟道电流的影响, 获得了最优化的异质栅结构. 模型所得结果与仿真结果及相关文献给出的结论一致, 证明了该模型的正确性. 该研究为异质多晶SiGe栅应变Si MOSFET的设计制造提供了有价值的参考. 关键词： 异质多晶SiGe栅 应变Si NMOSFET 表面势 沟道电流     

利用硅光电池测量硅单晶半导体材料的禁带宽度

以白炽灯为光源照射单晶硅光电池,测量在硅光电池前加不同截止波长的滤色片时的短路电流.通过短路电流和截止波长的关系,经拟合得到单晶硅材料的长波限,再利用半导体材料的长波限与半导体的禁带宽度Eg的关系,即Eg=hc/λ,计算得出其禁带宽度.     

Si/SiGe异质结构的硅盖层中应变对Raman谱特征的影响

应变Si/SiGe异质结构通过大剂量Ge离子注入并结合高温快速热退火制备而成。325 nm波长的紫外激光被用于调查应变Si盖层的Raman谱特征。实验发现,硅盖层中的张应变导致硅的520 cm-1的一级拉曼散射峰向低频方向偏移,峰的偏移程度反映硅盖层中横向张应力的大小约为12.5×108 N·m-2。硅盖层中的张应变并未导致1 555和2 330 cm-1的次级拉曼散射峰的变化。     

亚100 nm应变Si/SiGe nMOSFET阈值电压二维解析模型

本文基于二维泊松方程,建立了适用于亚100 nm应变Si/SiGe nMOSFET的阈值电压理论模型.为了保证该模型的准确性,同时考虑了器件尺寸减小所导致的物理效应,如短沟道效应,量子化效应等.通过将模型的计算结果与二维器件模拟器ISE的仿真结果进行对比分析,证明了本文提出的模型的正确性.最后,还讨论了亚100 nm器件中常规工艺对阈值电压的影响.该模型为亚100 nm小尺寸应变Si器件的分析设计提供了一定的参考. 关键词： 亚100nm 应变Si/SiGe nMOSFET 二维表面势 阈值电压     

利用电容-电压法研究GaN基双异质结发光二极管的结构特点

本文利用电容-电压法(C-V法)研究GaN基蓝光发光二极管的双异质结构,将测得的样品C-V曲线由变化中心处分为两部分,分别分析其PN结类型.接着通过液氮对二极管进行温度控制,得到不同温度下的C-V曲线及其对应的杂质浓度分布曲线,分析温度对两者的影响.最后由不同温度下的杂质浓度分布曲线,分析GaN基蓝光发光二极管的双异质结构.实验结果表明该GaN基双异质结蓝光二极管的PN结类型两边都为突变结,在不同温度下,样品的电容值随温度的升高呈增大趋势.双异质结构随温度的降低逐渐显著,当T=98 K时,双异质结构趋于理想情况.     

锗硅/硅异质结材料的化学气相淀积生长动力学模型

基于化学气相淀积(CVD)的Grove理论和Fick第一定律,提出并建立了锗硅(SiGe)/硅(Si)异质结材料减压化学气相淀积(RPCVD)生长动力学模型.与以前锗硅/硅异质结材料生长动力学模型仅考虑表面反应控制不同,本模型同时考虑了表面反应和气相传输两种控制机理,并给出了两种控制机理极限情况下的模型.本模型不仅适用于低温锗硅/硅应变异质结材料生长的表征,也适用于表征高温锗硅/硅弛豫异质结材料生长的表征.将模型计算值与实验结果进行了对比,无论是625℃低温下的应变SiGe的生长,还是900℃高温下的弛豫 关键词： SiGe/Si异质结材料 化学气相淀积生长动力学模型 Grove理论 Fick第一定律     

电容-电压法研究AlxGa1-xN/GaN异质结压电极化效应

制备了基于调制掺杂Al0.22Ga0.78N/GaN异质结的Pt/Al0.22Ga0.78N/GaN肖特基二极管.由于Al0.22Ga0.78N势垒层中的极化场不同,不同Al0.22Ga0.78N势垒层厚度的二极管的电容-电压特性显著不同.根据对样品电容-电压特性的数值模拟,在Al0.22Ga0.78N势垒层厚度为30nm和45nm的样品中,异质界面的极化电荷面密度为6.78×1012cm-2.在Al0.22Ga0.78N势垒层厚度为75nm的样品中,极化电荷面密度降为1.30×1012cm-2.这种极化电荷面密度的降低是由于GaN上Al0.22Ga0.78N势垒层由于厚度增加而产生应变的部分弛豫.本工作也提供了一种定量表征AlxGa1-xN/GaN异质结中极化电荷面密度的方法.     

表面钝化前后Al0.22Ga0.78N/GaN异质结势垒层应变的高温特性

用高分辨X射线衍射仪(HRXRD)研究了表面钝化前后Al0.22Ga0.78N/GaN异质结势垒层应变的高温特性,温度变化范围从室温到813K.结果表明,对未钝化的异质结,当测试温度高于523K时,Al0.22Ga0.78N势垒层开始出现应变弛豫;钝化后,在Al0.22Ga0.78N势垒层中会产生一个附加的平面拉伸应变,并随着温度的增加,势垒层中的平面拉伸应变会呈现出一个初始的增加,接着应变将减小,对100nm厚的Al0.22Ga0.78N势垒层,应变只是轻微地减小,但对于50nm厚的Al0.22Ga0.78N势垒层,则出现了严重的应变弛豫现象.     

C-V法研究温度对GaN基蓝光二极管pn结的影响

采用C-V法,根据C^-2-V曲线和C^-3-V曲线,并结合C-V幂律指数k,分析了T=25~-195℃温度范围内,温度变化对GaN基蓝光发光二极管pn结类型的影响。实验结果表明:当T为25℃和-50℃时,C^-2-V呈明显的线性关系,同时幂律指数k为0.5,说明该温度范围内的pn结类型为严格的突变结;而温度降低至-100℃时,k值变为0.45,说明pn结类型开始发生变化;当温度继续降低至-150℃和-195℃时,幂律指数k分别为0.30和0.28,说明pn结类型已经发生了变化,变为非突变非缓变结。造成这一现象的原因是低温导致的载流子冻析效应,以及晶体的缺陷和界面态形成的局域空间电荷区在低温环境下,影响了pn结原来的空间电荷分布,并改变了pn结类型。     

带隙法测定SiGe/Si材料的应变状态

从固体模型理论的结果出发，计算了生长于Si（100）衬底上x值小于085的Si_1-xGe_x合金材料（能带结构为类Si结构）的间接带隙与应变的关系，结 果表明，应变的S iGe材料的带隙和完全弛豫状态下材料的带隙之差与应变呈线性关系.基于这一结果，提出了 用测量带隙来间接测定SiGe/Si应变状态的方法.用带隙法和x射线双晶衍射法测量了不同应 变状态下的SiGe/Si多量子阱材料的应变弛豫度，两者可以较好的符合，表明带隙法测量SiG e应变弛豫度是可行的. 关键词： SiGe合金 应变 带隙     

Study of valence intersubband absorption in tensile strained Si/SiGe quantum wells

The hole subband structures and effective masses of tensile strained Si/Sil-yGey quantum wells are calculated by using the 6 × 6 k·p method. The results show that when the tensile strain is induced in the quantum well, the light-hole state becomes the ground state, and the light hole effective masses in the growth direction are strongly reduced while the in-plane effective masses are considerable. Quantitative calculation of the valence intersubband transition between two light hole states in a 7nm tensile strained Si/Si0.55Ge0.45 quantum well grown on a relaxed Si0.5Ge0.5 （100） substrates shows a large absorption coefficient of 8400 cm^-1.     

含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium(SiGe) heterojunction bipolar transistor(HBT) on thin silicon-on-insulator(SOI) has recently been demonstrated and integrated into the latest SOI BiCMOS technology.The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion,which is different from that of a bulk counterpart.A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation.The Early voltage shows a kink with the increase of the reverse base-collector bias.Large differences are observed between SOI devices and their bulk counterparts.The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design,the simulation and the fabrication of high performance SOI SiGe devices and circuits.     

Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel

A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Si量子信道 异质结构 CMOSFET 量子论 量子阱strained SiGe/Si, quantum well channel, heterostructure CMOSFET, poly-SiGe gateProject supported by the Preresearch from National Ministries and Commissions (Grant Nos 51408061104DZ01, 51439010904DZ0101).2/2/2006 12:00:00 AM2006-01-022006-03-16A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Sil-xGex layer for p-MOSFET and an electron quantum well channel in the tensile strained Si layer for n-MOSFET. The device possesses several advantages including： 1） the integration of electron quantum well channel with hole quantum well channel into the same vertical layer structure; 2） the gate work function modifiability due to the introduction of poly-SiGe as a gate material; 3） better transistor matching; and 4） flexibility of layout design of CMOSFET by adopting exactly the same material lays for both n-channel and p-channel. The MEDICI simulation result shows that p-MOSFET and n-MOSFET have approximately the same matching threshold voltages. Nice performances are displayed in transfer characteristic, transconductance and cut-off frequency. In addition, its operation as an inverter confirms the CMOSFET structured device to be normal and effective in function.     

A novel type of ultra fast and ultra soft recovery SiGe/Si heterojunction power diode with an ideal ohmic contact

A novel type of p^+(SiGe)－n^-－n^+ heterojunction switching power diode with high-speed capability is presented to overcome the drawbacks of existing power diodes. The improvement is achieved by using a p^+－n^+ mosaic layer as a substitute for the n^+ region in the conventional p^+(SiGe)－n^-－n^+ diode to realize an `ideal ohmic' contact for electrons and holes simultaneously. Compared with conventional p^+(SiGe)－n^-－n^+ diodes, the ideal ohmic contact p^+(SiGe)－n^-－n^+ diodes have about one third of the reverse recovery time and a half of peak reverse recovery current. Furthermore, the softness factor increases nearly two times and the leakage current decreases 1－2 orders of magnitude. These improvements are achieved without resorting special process step to lower the carrier lifetime and thus the devices could be easily integrated into power ICs. The Ge percentage content of p^+(SiGe) layer is an important parameter for the optimal device design.     

Weak avalanche multiplication in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

In this paper, we propose an analytical avalanche multiplication model for the next generation of SiGe silicon-on-insulator (SOI) heterojunction bipolar transistors (HBTs) and consider their vertical and lateral impact ionizations for the first time. Supported by experimental data, the analytical model predicts that the avalanche multiplication governed by impact ionization shows kinks and the impact ionization effect is small compared with that of the bulk HBT, resulting in a larger base-collector breakdown voltage. The model presented in the paper is significant and has useful applications in the design and simulation of the next generation of SiGe SOI BiCMOS technology.