基于DSP的直接数字频率合成器的研究和实现

作为微机继电保护测试仪核心部件之一,数字信号发生器的品质直接影响测试系统的整体性能。本文介绍了基于的高性能DSP芯片TMS320F2812实现直接数字频率合成器的工作原理、设计思想和软硬件结构;并提出一种优化的DDS实现方法,通过试验证明可进一步提高数字信号发生器的实时性与稳定性。该系统在一种新型微机继电保护测试仪中得到应用;实际应用表明：该类型测试仪可完成各类型的继保测试实验。     

有源电力滤波器中谐波提取的数字法实现

谐波提取的准确性和实时性是有源电力滤波器补偿电网谐波的关键环节。本文介绍了一种用新型数字信号处理器(DSP)TMS320F2407A实现的数字法谐波提取的设计,提出采用双采样频率的方法,解决了DSP有限字长、计算能力和谐波提取的高速、实时性之间的矛盾。利用MATLAB对谐波提取进行了仿真,并成功的应用于滞环跟踪型并联有源电力滤波器,仿真和实验结果证明数字法实现的谐波提取能够满足有源电力滤波器的准确性和实时性要求。     

基于DSP＋FPGA的核磁共振数据采集系统的设计

本文描述了一个以数字信号处理器系统为核心,以高速A/D转换器、（DDS）直接数字频率合成器、可编程逻辑门阵列FPGA、内含数控振荡器（NCO）的数字接收器为主体的核磁共振数据采集系统。根据自由感应回波信号低信噪比的特点,重点设计了差分输入的数据采集电路。     

数字锁相技术在逆变器并联系统中的应用

逆变器并联系统中各模块输出电压的频率、相位应时刻保持一致,这样才能保证并联系统的安全运行.针对输出母线电压频率可变(300～500 Hz)的并联系统,研究了采用TMS320F240型数字信号处理器(DSP)实现锁相的锁相环原理和方法;给出了硬件实现电路及算法流程图.实验结果验证了该方案的可行性和有效性.     

某末制导雷达VXI总线距离拖引干扰模拟器的设计

距离拖引干扰(RGPO)是现代电子战中干扰末制导雷达距离跟踪系统的一种常用方法.在研制某末制导雷达自动测试系统的过程中,为全面测试雷达的抗干扰能力,迫切需要研制出相应的距离拖引干扰模拟器.本文阐述了距离拖引干扰的基本理论,提出了一种基于VXI总线的距离拖引干扰模拟器的设计方案,该方案采用数字信号处理器(DSP)技术、可编程逻辑器件(CPLD)技术、直接数字频率合成(DDS)技术,实现了距离拖引干扰模拟器的小型化,具有实现简单、控制灵活、可靠性高等特点.经实验验证,该模拟器各项功能指标满足测试雷达性能的要求.     

功率因数校正（PFC）的数字控制方法

控制技术的数字化是开关电源的发展趋势。相对于传统的模拟控制技术，采用数字控制技术的功率因数校正(PVC)具有显的优点。详细讨论了采用数字信号处理器(DSP)作为控制核心时的设计事项和方法，最后提出了数字控制技术有待解决的问题。     

全数字永磁同步电机运动控制系统的设计

设计了一种基于数字信号处理器(TMS320LF2407A)和智能化功率模块(PM20CSJ060)的全数字永磁同步电机运动控制系统,重点介绍了系统的硬件结构和软件实现方法,并搭建实验平台,实验表明该系统具有良好的动态响应和调速特性。     

超音频感应加热电源在水产养殖中的应用

针对水产养殖传统加温采用锅炉(燃煤、燃油或用电)加热装置能耗高、功率低、污染严重、运行费用高等缺点,设计一款以电磁感应原理为基础的超音频感应加热装置。该装置以高速数字信号处理器TMS320F2812DSP为控制核心,完成了频率跟踪的数字锁相环(DPLL)设计,采用模糊PID控制方法对温度进行实时动态调整,实现了高精度数字化控制的恒温供水系统。样机试验表明,该装置加热速度快,精度高,效率高,节能环保。     

基于DSP的三相频率可调逆变电源设计

用TMS320LF2407ADSP芯片设计了一种采用SPWM调制策略的IGBT三相全桥逆变电路。对采用数字信号处理(DSP)实现的数字控制技术进行了深入研究,将SPWM调制策略与数字信号处理器(DSP)相结合,实现了输出频率可调,并通过仿真和试验验证了理论分析。     

多比特数字信号频率测量方法

文中提出一种可直接测量多比特数字信号频率的方法，叙述了基本原理及实施方法。此方法的特点是实施简单，成本低廉、精度高。当信号频率较高且量化的比特数较多时，上述优越性别明显。     

以TMS320C32为核心的控制器的设计

TMS32 0C32是一种通用型浮点数字信号处理器 ,可以作为高性能控制系统的核心CPU。讨论了在设计C32系统时应注意的一些问题 ,使系统中的C32性能能够得到充分发挥     

High-precision voltage-measuring method using fast sampled data for electric power systems

Control and protection equipment in power systems requires higher sensitivity and operational reliability to meet today's changing power system requirements. The voltage-measuring deviation requirement for advanced voltage and var control equipment is less than 0.1 percent under conditions of harmonic distortion in the voltage waveform and power-system frequency variation. Studies on digital signal processing suitable for electric power systems showed that these requirements are satisfied using fast sampling and very fast 32-bit floating point operations by a Digital Signal Processor (DSP). This paper describes the design philosophy of a high-precision power system voltage-measuring method using fast sampled data. In addition, total voltage-measuring deviation characteristics under a combination of the techniques are described along with digital filter characteristics, frequency-measuring deviation characteristics, frequency variation versus gain-compensation characteristics of a digital filter, and peak value operating principles.     

基于DSP及轴角数字转换器的直流无刷电机控制系统设计

设计了一种基于数字信号处理器(DSP)及轴角数字转换器AD2S80A的高精度直流无刷电机(BLDCM)控制系统,实现了电机转子位置的精确定位,同时为电机换相提供了准确的位置参考。整个系统集成度高、控制灵活、稳定性好。试验结果表明,该系统运行良好。     

基于新型全数字锁相环的同步倍频技术

为了实时跟踪电网频率的变化,提高直流输电系统中换流器触发脉冲控制精度,提出了一种基于新型全数字锁相环的同步倍频技术。该新型数字锁相环在传统数字锁相环的基础上加入了自适应模值控制模块,大幅提高了锁相速度和精度。在此基础上,利用近似补偿方法设计出的同步倍频模块能在高精度要求下对电网频率同步任意倍频,给换流器触发控制系统提供精准的时钟基准,提高相位控制精度,削弱换流器产生的非特征谐波。利用现场可编程门阵列(FPGA)为载体,在QUARTUSⅡ软件环境下,设计出了基于全数字锁相环的同步倍频装置,并通过软件仿真和实验测试验证了该技术的正确性和优越性。     

基于DSP和单片机双CPU结构的微机电动机保护

传统的微机保护，存在总计算速度较低和保护原理不够完善等问题。为了提高电动机保护装置的实时数据处理能力和实现较复杂的保护原理，采用数字信号处理器DSP(Digital Signal Proces-sor)负责数据计算处理和复杂保护原理的实现。简要介绍了由DSP和单片机构成的微机电动机保护装置的系统设计方案和硬件平台，并介绍了此装置的各种保护功能。单片机外围扩展电路较多，而其I／O口资源有限，因而采用了I^2C总线电路，从而较好地实现了装置监控功能。实践征明，该装置运算速度快，易实现复杂保护原理，较好地提高了保护装置性能。     

电网数字实时动态仿真系统的研制及其应用

介绍了电网数字实时动态仿真系统(DDRTS)的研制及其应用情况，突出了系统的设计和特点。DDRTS基于微机实时数字仿真，具有系统仿真分析和装置试验研究的功能。阐述了DDRTS研制中的关键技术和双处理器体系结构提高仿真速度的原理。大量系统仿真和试验研究的结果表明DDRTS是一套性能优越的全数字实时仿真系统。     

Digital input filters for measurement,control and protection in electric power systems

Power system control and protection equipment is subject to especially stringent sensitivity and operational reliability requirements. Projected digital signal processing systems suitable for electric power systems fulfill these requirements by means of fast sampling and digital filtering by a 32-bit floating point DSP (Digital Signal Processor). The sampling rate of 3 kHz is carefully selected in order to separate the power spectra of the A-D conversion output errors from the signal bandwidth. The new 12-bit A-D conversion unit equipped with a recursive-type digital filter achieved a high resolution equivalent to 14-bit conversion. This paper describes the design concept and the operating characteristics and illustrates applications to current differential relays, distance relays and power system controllers.     

Digital input filters for measurement,control and protection of electric power systems

Power system control and protection equipment has required higher sensitivity and operational reliability than conventional one. Studies of digital signal processing suitable for electric power systems fulfill this objective using fast sampling and digital filtering by a 32-bit floating point DSP (Digital Signal Processor). The sampling rate of 3 kHz is carefully selected in order to separate the power spectrums of the A-D conversion output errors from the signal bandwidth. The new 12-bit A-D conversion unit equipped with a recursive-type digital filter achieved the equivalent high resolution of 14-bit conversion. This paper describes the design concept and the characteristics showing applications to current differential relays, distance relays and power system controllers.     

Development of numerical linear algebra algorithms in dynamic fixed‐point format: a case study of Lanczos tridiagonalization

Proper range and precision analysis play an important role in the development of fixed‐point algorithms for embedded system applications. Numerical linear algebra algorithms used to find singular value decomposition of symmetric matrices are suitable for signal and image‐processing applications. These algorithms have not been attempted much in fixed‐point arithmetic. The reason is wide dynamic range of data and vulnerability of the algorithms to round‐off errors. For any real‐time application, the range of the input matrix may change frequently. This poses difficulty for constant and variable fixed‐point formats to decide on integer wordlengths during float‐to‐fixed conversion process because these formats involve determination of integer wordlengths before the compilation of the program. Thus, these formats may not guarantee to avoid overflow for all ranges of input matrices. To circumvent this problem, a novel dynamic fixed‐point format has been proposed to compute integer wordlengths adaptively during runtime. Lanczos algorithm with partial orthogonalization, which is a tridiagonalization step in computation of singular value decomposition of symmetric matrices, has been taken up as a case study. The fixed‐point Lanczos algorithm is tested for matrices with different dimensions and condition numbers along with image covariance matrix. The accuracy of fixed‐point Lanczos algorithm in three different formats has been compared on the basis of signal‐to‐quantization‐noise‐ratio, number of accurate fractional bits, orthogonality and factorization errors. Results show that dynamic fixed‐point format either outperforms or performs on par with constant and variable formats. Determination of fractional wordlengths requires minimization of hardware cost subject to accuracy constraint. In this context, we propose an analytical framework for deriving mean‐square‐error or quantization noise power among Lanczos vectors, which can serve as an accuracy constraint for wordlength optimization. Error is found to propagate through different arithmetic operations and finally accumulate in the last Lanczos vector. It is observed that variable and dynamic fixed‐point formats produce vectors with lesser round‐off error than constant format. All the three fixed‐point formats of Lanczos algorithm have been synthesized on Virtex 7 field‐programmable gate array using Vivado high‐level synthesis design tool. A comparative study of resource usage and power consumption is carried out. Copyright © 2015 John Wiley & Sons, Ltd.     

基于牛顿迭代法的高精度快速开方算法

针对全波傅氏算法中的开平方运算较耗时影响微机保护瞬动性问题,提出一种选取接近定点数开方真值的牛顿迭代初值的方法,该方法利用数字信号处理器(DSP)的移位指令、256个单元的查表技术和DSP的硬件乘法器,通过1次查表和1￣2次乘法运算,就能快速确定迭代误差小于2-9的迭代初值。在TIDSP集成开发平台上,运行牛顿迭代开平方汇编程序。运算结果表明:该算法对范围在00000004.0000H￣01FFFFFF.FFFFH的定点数抽样开方运算,迭代次数均不大于3次,就达到2-16以上迭代精度,且占用内存小,非常适合带有硬件乘法器的嵌入式微处理器实现。