联合判决估计在软判决Viterbi译码中的应用

该文利用相邻判决数据间的相互关系,提出了一种Viterbi截尾译码的改进算法,并将其应用到Turbo码的SOVA译码中。仿真表明,可以很好地降低复杂性和功耗。对Viterbi译码,可使留选存储的规模和功耗减少约20％,回溯单元的规模和功耗减少约30％。对Turbo码的SOVA译码,可使可靠值存储和输出单元的规模和功耗降低约15％,或迭代次数减少一半。     

Survivor memory reduction in the Viterbi algorithm

This paper presents a novel approach for implementation of the Viterbi algorithm, wherein survivor paths are generally kept in as low as one half of the storage required for traditional trace-back methods. Survivor memory reduction is obtained by storing only the useful part of the survivor paths. In other words, the redundancy in the survivor paths is removed. A decoder using this approach not only requires significantly less memory, but also runs faster than conventional decoders. Some instances of this approach are explicitly presented.     

Adaptive channel estimation and equalization for rapidly mobile communication channels

This paper presents a reduced-complexity maximum-likelihood sequence estimation receiver, based on the Viterbi algorithm (VA), suitable for rapidly fading mobile communication channels. The channel impulse response is expanded onto a set of basis sequences and time-invariant (TI) expansion parameters. The proposed receiver continuously estimates the TI expansion parameters directly within the metric calculation of the VA. At every time instant of the VA, the accumulated metrics of the survivor paths are compared, and the survivors whose metrics are lower than the average value of the accumulated survivor metrics are retained. The other survivors are discarded from the trellis. Then the sequences associated with the minimum survivor of the retained survivors are used to update the estimate of the TI expansion parameters. The convergence properties of the estimation algorithm are investigated, and the steady-state value of the mean square error of estimation is derived. The performance of the proposed receiver is evaluated in terms of the symbol-error probability and compared with other receivers. The effects of time offset and frequency offset on the performance of the receiver are studied.     

Design of Channel-Estimate-Dependent Space–Time Block Codes

Adaptive Channel Estimation and Equalization for Rapidly Mobile Communication Channels The paper presents a reduced-complexity maximum-likelihood sequence estimation receiver, based on the Viterbi algorithm (VA), suitable for rapidly fading mobile communication channels. The channel impulse response is expanded onto a set of basis sequences and time-invariant (TI) expansion parameters. The proposed receiver continuously estimates the time instant of the VA, the accumulated metrics of the survivor paths are compared, and the survivors whose metrics are lower than the average value of the accumulated survivor metrics are retained. The other survivors are used to update the estimate of the TI expansion parameters. The convergence properties of the estimation algorithm are investigated, and the steady-state value of the mean square error or estimation is derived. The performance of the proposed receiver, in terms of the symbol-error probability, is compared with other receivers. The effects of time offset and frequency offset on the performance of receiver are studied.     

Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder

Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. This limitation also incurs power and silicon area overhead. This paper presents a modified adaptive Viterbi algorithm, referred to as the relaxed adaptive Viterbi algorithm, that completely eliminates the global best survivor path metric search operation. A state-parallel decoder VLSI architecture has been developed to implement the relaxed adaptive Viterbi algorithm. Using convolutional code decoding as a test vehicle, we demonstrate that state-parallel relaxed adaptive Viterbi decoders, versus Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and very high throughput     

An Efficient In-Place VLSI Architecture for Viterbi Algorithm

This paper presents a novel design of Viterbi decoder based on in-place state metric update and hybrid survivor path management. By exploiting the in-place computation feature of the Viterbi algorithm, the proposed design methodology can result in high-speed and modular architectures suitable for those Viterbi applications with large constraint length. This feature is not only applied to the design of highly regular ACS units, but also exploited in the design of trace-back units for the first time. The proposed hybrid survivor path management based on the combination of register-exchange and trace-back schemes cannot only reduce the number of memory operations, but also the size of memory required. Compared with the general hybrid trace-back structure, the overhead of register-exchange circuit in our architecture is significantly less. Therefore, the proposed architecture can find promising applications in digital communication systems where high-speed large state Viterbi decoders are desirable.     

Path diversity reception employing steering vector arrays andsequence estimation techniques for ISI channels

We propose a path diversity reception technique that uses steering vector arrays and Viterbi algorithm-based sequence estimation techniques to cope with severe intersymbol interference (ISI). The proposed scheme suppresses some delayed paths with spatial and temporal processing based on the single constraint sample matrix inversion algorithm to reduce excess ISI for sequence estimation. The path diversity branches are weighted in proportion to the quality of the array output signals and then combined via the branch-metric-combining (BMC) Viterbi algorithm to estimate the most likely transmitted sequence. Maximum likelihood sequence estimation, limited-state sequence estimation, and decision-feedback sequence estimation are examined for their suitability as estimation techniques. Consequently, the proposed scheme is sufficient for managing various kinds of channel models. Thus, the proposed scheme is suitable for high-speed time-division multiple access (TDMA) mobile radio systems, because, in this kind of transmission, fading can be presumed to be nearly quasi-static during the burst, and the delayed paths are spread over several symbols     

Memory savings in Viterbi decoders for (n, 1, m) convolutional codes

A novel approach to achieve memory savings in MLD Viterbi decoders is proposed. It is based on tracking a code's trellis survivor paths in the decoding decision process using a backward labels technique, rather than the traditional forward labels technique, and exploiting a shift register property of the trellis. Savings of the order of 20% of memory requirements in (n, 1, m) convolutional codes are achievable without loss of decoding performance.     

Optimally regularized channel tracking techniques for sequenceestimation based on cross-validated subspace signal processing

New methods for maximum-likelihood sequence estimation based on the Viterbi algorithm (VA) are presented. In the proposed scheme, the channel estimator and the Viterbi processor operate concurrently. At any given time-step, the sequence provided to the channel estimator comes from the survivor with the best metric value. These already known modifications of the traditional decision-directed VA cause large variance in the estimated channel coefficients. In fact, sequences with a high error rate may be used to perform estimation, and also the adjustment term of the channel tracking algorithm may exhibit abrupt changes caused by a “survivor swap”, (that is by the event in which a different survivor has the best metric at step n, with respect to the step n-1). The proposed regularization procedure forces the channel vector to lie in the appropriate a priori known subspace: while the variance decreases, a certain amount of bias is introduced. The variance-bias tradeoff is then automatically adjusted by means of a cross-validation “shrinkage” estimator, which is at the same time optimal in a “small sample” predictive sum of squares sense and asymptotically model mean squared-error optimal. The method is shown by means of hardware experiments on a wide-band base station to be extremely more effective than per survivor processing, minimum survivor processing, and traditional decision directed approaches     

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.     

Two decoding algorithms for tailbiting codes

The paper presents two efficient Viterbi decoding-based suboptimal algorithms for tailbiting codes. The first algorithm, the wrap-around Viterbi algorithm (WAVA), falls into the circular decoding category. It processes the tailbiting trellis iteratively, explores the initial state of the transmitted sequence through continuous Viterbi decoding, and improves the decoding decision with iterations. A sufficient condition for the decision to be optimal is derived. For long tailbiting codes, the WAVA gives essentially optimal performance with about one round of Viterbi trial. For short- and medium-length tailbiting codes, simulations show that the WAVA achieves closer-to-optimum performance with fewer decoding stages compared with the other suboptimal circular decoding algorithms. The second algorithm, the bidirectional Viterbi algorithm (BVA), employs two wrap-around Viterbi decoders to process the tailbiting trellis from both ends in opposite directions. The surviving paths from the two decoders are combined to form composite paths once the decoders meet in the middle of the trellis. The composite paths at each stage thereafter serve as candidates for decision update. The bidirectional process improves the error performance and shortens the decoding latency of unidirectional decoding with additional storage and computation requirements. Simulation results show that both proposed algorithms effectively achieve practically optimum performance for tailbiting codes of any length.     

New Soft Output Viterbi Algorithm for Mobile Communication System

Soft output Viterbi algorithm(SOVA) is a turbo decoding algorithm that is suitable for hardware implementation. But its performance is not so good as maximum a posterior probability(MAP) algorithm. So it is very important to improve its performance. The non-correlation between minimum and maximum likelihood paths in SOVA is analyzed. The metric difference of both likelihood paths is used as iterative soft information, which is not the same as the traditional SOVA. The performance of the proposed SOVA is demonstrated by the simulations. For 1024-bit frame size and 9 iterations with signal to noise ratio from 1dB to 4dB, the experimental results show that the new SOVA algorithm obtains about more 0.4dB and 0.2dB coding gains more than the traditional SOVA and Bi-SOVA algorithms at bit error rate(BER) of 1×10~ -4 , while the latency is only half of the Bi-direction SOVA decoding.     

A continuously adaptive MLSE receiver for mobile communications:algorithm and performance

The paper presents a Euclidean distance maximum likelihood sequence estimation (MLSE) receiver, based on the Viterbi algorithm (VA), suitable for fading and noisy communications channels, as that specified by the Group Special Mobiles (GSM). In a mobile cellular system, the fast varying channel characteristics, due to the fading and Doppler effects, require adaptive methods to update the channel coefficients to the MLSE receiver. The proposed technique continuously estimates the channel characteristics directly within the metric calculation of the VA. At each step of the VA, the sequence associated to the path with the best metric value (minimum-survivor method) among the survivor paths is used to update the channel estimate (employing conventional adaptive algorithms) throughout the entire informative sequence. However, the detection of the transmitted data sequence is performed by the VA only at the end of each burst. The proposed technique allows simpler receiver implementation and the simulation results show a good performance of this adaptive MLSE receiver in typical GSM environments     

Viterbi decoder without carrier recovery

A novel Viterbi algorithm of low complexity without carrier recovery is proposed. The most important modification is that the decision metric for surviving paths is not the cumulated variable but its amplitude. Simulation results of its application to MDPSK and convolutional code show negligible performance loss     

Iterative Viterbi algorithm: implementation issues

We address several issues for implementing the iterative Viterbi decoder. We show that 3-bit branch metric quantization, 7- or 8-bit state metric precision, and a survivor length of five times the constraint length yields little degradation for the iterative Viterbi algorithm (IVA). Our results show that without changing the VA hardware (except adding some additional circuits), the error performance of several standard systems can be significantly improved.     

An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

A large portion of silicon area and the energy consumed by the Viterbi decoder (VD) is dedicated to the survivor memory and the access operations associated with it. In this work, an efficient pre-traceback architecture for the survivor-path memory unit (SMU) of high constraint length VD targeting wireless communication applications is proposed. Compared to the conventional traceback approach which is based on three kinds of memory access operations: decision bits write, traceback read, and decode read, the proposed architecture exploits the inherent parallelism between the decision bit write and decode traceback operation by introducing pre-traceback operation. Consequently, the proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, compared to the conventional 2-pointer traceback algorithm, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback architecture achieves up to 11.9% energy efficiency and 21.3% area saving compared to the conventional traceback architecture for typical wireless applications.     

卷积码Viterbi译码算法的FPGA实现

探讨了卷积码Viterbi译码的FPGA实现问题。在Viterbi译码算法中，提出了减少路径量度的位数和流水线回索法的幸存路径等方法，能有效地减少存储量、降低功耗、提高速度，使得K=7的Viterbi译码算法可在以单片FPGA为主的器件上实现。     

Limited search trellis decoding of convolutional codes

The least storage and node computation required by a breadth-first tree or trellis decoder that corrects t errors over the binary symmetric channels is calculated. Breadth-first decoders work with code paths of the same length, without backtracking. The Viterbi algorithm is an exhaustive trellis decoder of this type; other schemes look at a subset of the tree or trellis paths. For random tree codes, theorems about the asymptotic number of paths required and their depth are proved. For concrete convolutional codes, the worst case storage for t error sequences is measured. In both cases the optimal decoder storage has the same simple dependence on t. The M algorithm and algorithms proposed by G.J. Foschini (ibid., vol.IT-23, p.605-9, Sept. 1977) and by S.J. Simmons (PhD. diss., Queens Univ., Kingston, Ont., Canada) are optimal, or nearly so; they are all far more efficient than the Viterbi algorithm     

一种高速Viterbi译码器幸存路径管理模块的改进结构

针对高速Viterbi译码器的高速,低延迟,低电路复杂度的要求,在分段执行的Hybrid Trace Forward方法的基础上,提出了一种新的幸存路径管理模块(SMU)结构—固定段长的结构。对于(m,n,k)的Viterbi译码器,约束长度为k,则固定段长为k-1,既节省了存储空间,又消除了回溯过程,从而降低了延迟时间和电路复杂度。文中设计了一个(2,1,7)Viterbi译码器的SMU模块,采用固定长度为6的结构。相比于传统的分段执行的Hybrid Trace Forward结构,译码延迟减小了17%,输出数据间隔减小了33%,并且省去了存储器的使用。     

An adaptive per-survivor processing algorithm

We propose an adaptive and parameter-independent per-survivor processing algorithm to improve the receiver performance on time-varying channels. With a variable step size for a plurality of survivor paths, this new method eliminates the dependency of all the survivor paths and improves the convergence rate of channel estimation.