A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET

A Double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) is emerging device architecture in sub-nanometer regime. The performance of DG MOSFET can be ameliorated by gate and channel engineering. The concept of graded-channel gate-stack (GCGS) and dual-material (DM) are incorporated in DG MOSFET. A two-dimensional (2D) analytical surface potential model for GCGS DMDG MOSFET is developed based on the solution of Poisson’s equations with appropriate boundary conditions. It has been found that analytically modeled data is in good degree of agreement with numerically simulated data. The combination of both DM and GC concept introduces a step variation in potential profile at the junction of both materials in channel region and ameliorates the short channel effects (SCEs). A suppressed subthreshold swing (SS) and drain induced barrier lowering (DIBL) has been observed in the device due to an elevated average velocity of carrier and reduced drain field effect by the use of DM and GC with GS. Further, analog/RF characteristics such as transconductance generation factor (TGF), cut-off frequency (f_T) and transconductance frequency product (TFP) have been examined with different GS high-k dielectrics. The numerically simulated data has been extracted using 2D ATLAS device simulator.     

Interface Trap Charge Induced Threshold Voltage Modeling of WFE High-K SOI MOSFET

Silicon - The present endeavor attempts to develop an explicit threshold voltage model of linearly graded work function engineered Silicon-On-Insulator MOSFET considering the effects of localized...     

Analytical Study of Effect of Channel Doping on Threshold Voltage of Metal Gate High-k SiGe MOSFET

The paper reports the analytical model for the analysis of the effects of channel doping on the threshold voltage. A silicon germanium p-MOSFET with high-k dielectric material along with a metal gate is used for the analysis. The presented model considers the short channel effects, junction depth, doping of the layers and metal gate work function. Results are validated with the 22 nm device geometry. The MOSFET with reduced channel doping reflects the corresponding reduction in the threshold voltage. The model can effectively analyze the SiGe p-MOSFET for device designing in the nanometer regime.     

Analytical Subthreshold Model of Electrical Field-Effect for the Capacitance in Cylindrical Surrounding Double-Gate MOSFET Paradigm

Silicon - A novel extensive subthreshold model of Cylindrical Surrounding Double-Gate (CSDG) MOSFET with gate-bias voltage and source/drain drops using the fundamental Double-Gate (DG) MOSFET has...     

Threshold Voltage Modeling of tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs)

Silicon - In this work, a threshold voltage model of Tri-Gate Schottky-Barrier (TGSB) MOSFET is presented by coupling threshold voltage models of symmetric and asymmetric double-gate...     

Dual-Metal Double-Gate with Low-k/High-k Oxide Stack Junctionless MOSFET for a Wide Range of Protein Detection: a Fully Electrostatic Based Numerical Approach

Silicon - We investigate the performance of a dielectric modulated dual-metal double-gate with low-k/high-k oxide stack junctionless MOSFET (DM-DG-LK/HK-S JL-MOSFET) based sensor device for...     

Analytical Modeling of Surrounding Gate Junctionless MOSFET Using Finite Differentiation Method

Silicon - In this paper, a novel two-dimensional analytical model for threshold voltage on Dual Material Surrounding Gate Junctionless MOSFET is proposed. The analytical study is aimed at...     

A Novel Approach to Investigate the Impact of Hetero-High-K Gate Stack on SiGe Junctionless Gate-All-Around (JL-GAA) MOSFET

Silicon - It is a well-known fact that the gate stacking is used to improve the electrostatic behavior of Si0.5Ge0.5 Junctionless Gate-All-Around (JL-GAA) MOSFETs. In gate stacking, the high-k...     

An Accurate Model of Threshold Voltage and Effect of High-K Material for Fully Depleted Graded Channel DMDG MOSFET

Silicon - In this study, an accurate model for threshold voltage of graded channel dual material double gate (GCDMDG) structure metal-oxide-semiconductor (MOS) has been established and a...     

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Silicon - This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has...     

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

Silicon - The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel...     

Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)

Silicon - In the present paper, a threshold voltage model of short channel silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) has been presented. The model includes the...     

A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs

Silicon - This present article interprets the analytical models of central channel potential, the threshold voltage, and subthreshold current for Graded-Doped Junctionless-Gate-All-Around...     

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Silicon - Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET has been explored for low power applications. This paper presents an analytical model of...     

Investigation of Subthreshold Characteristics of Negative Capacitance Single-Active Layer Double-Gate (NC-SALDG) Thin-Film Transistor (TFT)

Silicon - In this paper, for the first time, the performance evaluation of negative capacitance single-active layer double-gate (NC-SALDG) TFT is presented. In the proposed NC-SALDG TFT, amorphous...     

Quantum Analytical Model for Lateral Dual Gate UTBB SOI MOSFET for Analog/RF Performance

Silicon - This paper presents a quantum analytical modeling of UTBB SOIMOSFET as lateral dual gate for the first time. In this paper, a 2-dimensional analytical modeling of electric field...     

Analytical Modeling of Short-Channel Fully-Depleted Triple Work Function Metal Gate (TWFMG) SOI MESFET

Silicon - In this paper, a new structure: triple work function metal gate SOI MESFET, intended for integration into the deep-submicron CMOS technology, is proposed. The gate of the device consists...     

Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling

Silicon - Recently, transistors with an underlapped gate structure have been widely studied to overcome several challenges associated with nanoscale devices. In this work, underlap region is...     

A 2-D Analytical Modeling of Dual Work Function Metal Gate MOSFET Using High-K Gate Dielectric with Enhanced RF/Analog Performance for Low Power Applications

A 2-dimensional electrostatic potential modeling of fully depleted channel, with high-k based dual work function double gate (DWFDG) MOSFET, has been devel     

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Silicon - In this paper, we comprehensively assess the unique features, feasibility and limitations of dual material gate fin field effect transistor for tuning the threshold voltage in nanoscale...