NiSi/Si界面的剖面透射电镜研究

采用不同硅化工艺制备了NiSi薄膜并用剖面透射电镜(XTEM)对样品的NiSi/Si界面进行了研究.在未掺杂和掺杂(包括As和B)的硅衬底上通过物理溅射淀积Ni薄膜,经快速热处理过程(RTP)完成硅化反应.X射线衍射和喇曼散射谱分析表明在各种样品中都形成了NiSi.还研究了硅衬底掺杂和退火过程对NiSi/Si界面的影响.研究表明:使用一步RTP形成NiSi的硅化工艺,在未掺杂和掺As的硅衬底上,NiSi/Si界面较粗糙;而使用两步RTP形成NiSi所对应的NiSi/Si界面要比一步RTP的平坦得多.高分辨率XTEM分析表明,在所有样品中都形成了沿衬底硅〈111〉方向的轴延-NiSi薄膜中的一些特定晶面与衬底硅中的(111)面对准生长.同时讨论了轴延中的晶面失配问题.     

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

We explore a novel integration approach that introduces valence-mending adsorbates such as sulfur (S) or selenium (Se) by ion implantation and prior to nickel silicidation for the effective reduction of contact resistance and Schottky barrier (SB) height at the NiSi/n-Si interface. While a low SB height of ~0.12 eV can be obtained for NiSi formed on S-implanted n-Si, the insertion of a 1000degC anneal prior to silicidation leads to S out-diffusion and loss of SB modulation effects. We demonstrate that Se-implanted Si does not suffer from Se outdiffusion even after a 1000degC anneal, and subsequent Ni silicidation formed an excellent ohmic contact with a low SB height of 0.13 eV. Se segregation at the NiSi/n-Si (100) interface occurred. Implantation of Se and its segregation at the NiSi/n-Si interface is a simple and promising approach for achieving reduced SB height and contact resistance in future high-performance n-channel field-effect transistors.     

Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications

The work function of fully nickel-silicided polysilicon was investigated. The midgap work function (4.7 eV) was obtained for undoped mononickel-silicide (NiSi). It was shown that the implantation of both arsenic and antimony into the polysilicon before silicidation reduces the NiSi work function, and the change in work function is greater for antimony than for arsenic. The pile-up of these species at the oxide interface during the nickel silicidation is demonstrated to be the physical mechanism responsible for the work function shift. Both species activations before silicidation and silicidation conditions were found to affect the NiSi work function shift significantly. The nonactivated species have minimum effect and incomplete silicidation can have maximum work function shift. The doping effect of indium on the NiSi work function is reported for the first time. A shift of /spl sim/0.14 eV toward the valence band was obtained for 2.6-nm oxide capacitors. It was found that the work function shift caused by the indium doping is saturated at a relatively low dose, which may be related to the low solid solubility of indium in polysilicon.     

Improvement of thermal stability of Ni silicide on N-Si by direct deposition of group III element (Al, B) thin film at Ni/Si interface

The direct deposition of a thin Al or B layer at Ni/Si interface was proposed as a new method to solve a problem of degraded thermal stability of Ni silicide on heavily doped N⁺-Si substrates. Significant improvement of thermal stability evaluated by the sheet resistance vs. silicidation temperature properties was observed. The improvement is attributed to suppression of agglomeration of the silicide layers. The Al layer was effective only when it was located at the Ni/Si interface before the silicidation process. The deposited Al and B layers under Ni layer segregated at the surface after the silicidation process. The use of B layer was preferable to control the phase transition from NiSi to NiSi₂.     

Reduction of Leakage and Low-Frequency Noise in MOS Transistors Through Two-Step RTA of NiSi-Silicide Technology

A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-$muhboxm$gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The$ n^+- p$junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in off-state leakage$(sim!hbox5times)$and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors.     

Silicidation of Ni(Yb) Film on Si(001)

The influence of the addition of Yb to Ni on the silicidation of Ni was investigated. The Ni(Yb) film was deposited on a Si(001) substrate by co-sputtering, and silicidation was performed by rapid thermal annealing (RTA). After silicidation, the sheet resistance of the silicide film was measured by the four-point probe method. X-ray diffraction and micro-Raman spectroscopy were employed to identify the silicide phases, and the redistribution of Yb after RTA was characterized by Rutherford backscattering spectrometry and Auger electron spectroscopy. The influence of the Yb addition on the Schottky barrier height (SBH) of the silicide/Si diode was examined by current–voltage measurements. The experimental results reveal that the addition of Yb can suppress the formation of the high-resistivity Ni₂Si phase, but the formation of low-resistivity NiSi phase is not affected. Furthermore, after silicidation, most of the Yb atoms accumulate in the surface layer and only a small number of Yb atoms pile up at the silicide/Si(001) interface. It is believed that the accumulation of a small amount of Yb at the silicide/Si(001) interface results in the SBH reduction observed in the Ni(Yb)Si/Si diode.     

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:Ni2Si, and Ni31Si12) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁ Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS     

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi₂ were possible for thicker films depending on anneal temperature and time. Activation energy of 2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi₂ is higher than for morphological degradation.     

非晶化注入技术在NiSi SALICIDE工艺中的应用

在pn结形成之后借助非晶化Si离子注入技术可以将结表面Si单晶层非晶化. 作者研究了这种非晶化处理对Ni硅化反应的影响. 实验发现，非晶化处理可以促进Ni在低温下与衬底Si的反应，而且在低温下Ni/Si可以直接反应形成NiSi. 实验结果表明这种非晶化未对硅化反应过程中杂质的再分布产生影响，但是剖面透射电镜分析表明，这种非晶化所需能量需要合理优化.     

Ni(Pt)Si硅化物温度稳定性的研究

对比研究了夹层结构N i/P t/N i分别与掺杂p型多晶硅和n型单晶硅进行快速热退火形成的硅化物薄膜的电学特性。实验结果表明,在600~800°C范围内,掺P t的N iS i薄膜电阻率低且均匀,比具有低电阻率的镍硅化物的温度范围扩大了100~150°C。依据吉布斯自由能理论,对在N i(P t)S i薄膜中掺有2%和4%的P t样品进行了分析。结果表明,掺少量的P t可以推迟N iS i向N iS i2的转化温度,提高了镍硅化物的热稳定性。最后,制作了I-V特性良好的N i(P t)S i/S i肖特基势垒二极管,更进一步证明了掺少量的P t改善了N iS i肖特基二极管的稳定性。     

The reaction characteristics of ultra-thin Ni films on undoped and doped Si (100)

Reaction characteristics of ultra-thin Ni films (5 nm and 10 nm) on undoped and highly doped (As-doped and B-doped) Si (100) substrates are investigated in this work. The sheet resistance (Rs) measurements confirm the existence of a NiSi salicidation process window with low Rs values within a certain annealing temperature range for all the samples except the one of Ni(5 nm) on P⁺-Si(100) substrate (abnormal sample). The experimental results also show that the transition reaction to low resistivity phase NiSi is retarded on highly doped Si substrates regardless of the initial Ni film thickness. Micro-Raman and x-ray diffraction (XRD) measurement show that NiSi forms in the process window and NiSi₂ forms in a higher temperature annealing process for all normal substrates. Auger electron spectroscopy (AES) results for the abnormal sample show that the high resistivity of the formation film is due to the formation of NiSi₂.     

镍硅化物生成的TEM原位研究

蒸涂法获得的Si-Ni界面在室温到800℃下热处理,并用透射式电子显微镜对它进行原位研究。在化学清洗的洁净的Si(100)及(111)面上生成了Ni2Si,NiSi和NiSi2系列。实验表明,在真空度为110-6mmHg,温度为650℃时,化学清洗的Si表面上生成了SiC;各种镍硅化物的出现不是在某一确定温度;在Si(111)面上外延生长镍硅化物比在(100)面上容易。     

Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers

Dual-work-function metal gates fabricated by full silicidation (FUSI) of Co-Ni bi-layer with doped poly-Si were investigated for the first time, along with single-metal FUSI systems of CoSi/sub 2/ and NiSi. Complete conversion of poly-Si into Co-Ni alloy silicided metal gate (FUSI) Co/sub x/Ni/sub 1-x/Si/sub 2/ was demonstrated. Although a linear relationship between work function and Ni percentage was observed for FUSI of undoped poly-Si systems, the work functions of doped Co/sub x/Ni/sub 1-x/Si/sub 2/ are almost identical to those of doped NiSi FUSI metal gates. The alloy FUSI metal gates explored in this letter provide a new class of metal gates for CMOS devices that combine the advantages of both NiSi and CoSi/sub 2/, i.e., proper work function tunability of NiSi and high thermal stability of CoSi/sub 2/.     

Pt层对Ni/Si(100)固相反应NiSi薄膜高温稳定性的增强效应

研究了顺次淀积在Si(100)衬底上的Ni/Pt和Pt/Ni的固相硅化反应．研究发现,当1nm Pt作为中间层或覆盖层加入Ni/Si体系中时,延缓了NiSi向NiSi2的转变,相变温度提高．对于这种双层薄膜体系,800℃退火后,XRD测试未检测到NiSi2相存在;850℃退火后的薄膜仍有一些NiSi衍射峰存在．800℃退火后的薄膜呈现较低的电阻率,在23—25μΩ*cm范围．上述薄膜较Ni/Si直接反应生成膜的热稳定性提高了100℃以上．这有利于NiSi薄膜材料在Si基器件制造中的应用．     

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

We report a new method of forming nickel silicide (NiSi) on n-Si with low contact resistance, which achieves a Schottky barrier height of as low as 0.074 eV. Antimony (Sb) and nickel were introduced simultaneously and annealed to form NiSi on n-Si (100). Sb dopant atoms were found to segregate at the NiSi/Si interface. The devices with Sb segregation show complete nickel monosilicide formation on n-Si (100) and a close-to-unity rectification ratio. The rectification ratio R_c is defined to be the ratio of the forward current to the reverse current, where the forward and reverse currents are measured using forward and reverse bias voltages, respectively, having the same magnitude of 0.5 V. This process is also compatible and easily integrated in a CMOS fabrication process flow.     

Ti中间层对超薄Ni膜硅化反应特性的影响

在多种Si衬底上利用离子束溅射淀积超薄Ni膜以及Ni/Ti双层膜，经过快速热退火处理完成薄膜的固相硅化反应，通过四探针法、微区喇曼散射法和俄歇深度分布测试法研究了Ti中间层对Ni硅化反应的影响. 实验结果证明Ti中间层抑制了集成电路生产最需要的NiSi相的形成.     

深槽Ni(Pt)Si/Si肖特基二极管特性研究

采用15nmNi/1.5nmPt/15nmNi/Si结构在600～850°C范围内经RTP退火的方法形成Ni(Pt)Si薄膜,其薄膜电阻低且均匀一致。比形成较低电阻率的NiSi薄膜的温度提高了150°C。在850°CRTP退火后形成的Ni(Pt)Si/Si肖特基势垒二极管I-V特性很好,其势垒高度ΦB为0.71eV,改善了肖特基二极管的稳定性。实验表明在肖特基二极管中引入深槽结构,可以大幅度地提高其反向击穿电压。在外延层浓度为5E15cm-3时,深槽器件的击穿电压可以达到80V,比保护环器件高约30V。     

Impacts of Dopant Segregation on the Performance and Interface-State Density of the MOSFET With FUSI NiSi Gate

MOSFET characteristics of NiSi fully silicidation of polysilicon gates are found to be influenced by preimplanted dopant. Dopant segregation induced by silicidation at gate/oxide interface is observed to affect threshold voltage, subthreshold swing, effective mobility, and interface characteristics. The degradation of MOSFET characteristics in B-doped NiSi metal gate is found to be related to increasing interface-state density due to silicidation-induced impurity segregation     

两步生长和直接生长GaAs/Si单晶薄膜的比较

报道了采用热壁外延(HWE)技术,在(100),(111)和(211)三种典型Si表面通过两步生长和直接生长法制备GaAs单晶薄膜,经过拉曼光谱、霍尔测试和荧光光谱分析比较,得出结论:(1)相同取向Si衬底,两步生长法制备的GaAs薄膜结晶质量比直接生长法制备的GaAs薄膜的要好;(2)采用HWE技术在Si上异质外延GaAs薄膜,其表面缓冲层的生长是降低位错、提高外延质量的基础;(3)不同取向Si衬底对GaAs外延层结晶质量有影响, (211)面外延的GaAs薄膜质量最好,(100)面次之,(111)面最差.     

Supersonic jet epitaxy of silicon carbide on silicon using methylsilane

Cubic SiC thin films have been epitaxially grown on silicon substrates using the single source precursor methylsilane (H₃Si–CH₃). Single phase films were grown by supersonic jet epitaxy (SJE) at temperatures as low as 560°C on Si(111) and 600°C on Si(001). Growth rates and crystal quality were found to be strongly dependent on substrate temperature and methylsilane kinetic energy. Films were characterized by X-ray diffraction (XRD) and cross-sectional transmission electron microscopy (XTEM).