OFDM系统同步算法研究及其VLSI实现

针对正交频分复用（OFOM, Orthogonal Frequency Division Multiplex）无线传输系统,提出并设计了一种适用于802．11a标准前导序列的同步算法。首先基于接收基带数据能量判断信道空闲状态,再计算数据归一化自相关值检测帧起始位置,最后利用基带数据与参考训练序列的互相关运算检测OFDM符号的起始位置,实现同步功能。算法的硬件实现采用移位加和流水线技术来提高系统的性能与效率。实践表明,所提算法能有效地实现同步并且硬件实现复杂度低,适合于超大规模集成电路（VLSI,Very LargeScale Integration）的实现。     

基于偏心Preissmann格式的高速互连线分析

 将偏心Preissmann格式应用于高速电路互连线分析,导出一种互连线离散模型.通过调整偏心参数,可以获得二阶精度的差分格式.数值仿真表明,该方法能够应用于一般互连线的瞬态分析,改善间断之后的数值扰动现象,并与特征法进行了比较,说明了方法的有效性.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

一种考虑自热效应的互连线缓冲器插入优化模型

Considering the self-heating effect,an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented.Based on the proposed resistance model and according to the trade-off theory,a novel optimization analytical model of delay,power dissipation and bandwidth is derived.The proposed optimal model is verified and compared based on 90 nm,65 nm and 40 nm CMOS technologies.It can be found that more optimum results can be easily obtained by the proposed model.This optimization model is more accurate and realistic than the conventional optimization models,and can be integrated into the global interconnection design of nano-scale integrated circuits.     

Process and device modeling for VISI

The appearance of Very Large Scale Integration caused a pronounced interest in concentrating on process and device modeling. The fundamental properties which represent the basis for all device modeling activities are summarized. The sensible use of physical and technological parameters is discussed and the most important physical phenomena which are required to be taken into account are scrutinized. The assumptions necessary for finding a reasonable trade-off between efficiency and effort for a model synthesis are recollected. Methods to bypass limitations induced by these assumptions are pin-pointed. Formulae that are applicable in a simple and easy way for the physical parameters of major importance are presented. The necessity of a careful parameter-selection, based on physical information, is shown. Some glimpses on the numerical solution of the semiconductor equations are given. The discretisation of the partial differential equations with finite differences is outlined. Linearisation methods and algorithms for the solution of large sparse linear systems are sketched. Results of our two dimensional MOSFET model — MINIMOS — are discussed. Much emphasis is laid on the didactic potential of such a complex high order model.     

锯齿型单壁碳纳米管的光电性质

应用基于广义梯度近似的密度泛函理论中的简化广义梯度近似方法(PBE)对(7,0)至(18,0)锯齿型单壁碳纳米管在极化与非极化条件下从紫外波段到近红外波段的光电性质分别做了理论计算,得到了锯齿型碳纳米管的各光学常数峰值和各光学常数峰值所对应的波长与其手性参数n之间的对应关系和变化趋势。结果表明:除反射率和损耗外的各光学常数的峰值是随着n的增大而减小的;除反射率峰值对应波长外,其它光学常数的峰值对应的波长值随着n的增大逐渐趋于一个恒定值。     

半导体型单壁碳纳米管的电子输运特性

采用基于密度泛函理论的非平衡格林函数法(Non-equilibrium Green functions,NEGF),对耦合于两个面心立方间的Al(111)电极间的(8,0)碳纳米管(Carbon nanotube,CNT)传输特性进行了计算。结果表明,在小偏压下(-40～40 mV),碳纳米管伏安特性与孤立碳纳米管的接近为零不同,而是接近为线性,这是耦合导致碳纳米管能级移动的结果。     

MPEG-4运动补偿的VLSI结构设计

针对MPEG．4解码中运动补偿控制复杂、数据吞吐量大、实现较困难,提出了一种适合MPEG-4的运动补偿硬件实现方案,解决了时序分配、输入输出控制等较难处理的问题。此方案已经在Xilinx ISE6．li集成开发环境下,采用了VHDL进行描述,并使用了电子设计自动化（EDA）工具进行了模拟和验证。仿真和综合结果表明,设计的运动补偿处理器逻辑功能完全正确,而且可以满足MPEG-4 Core Profiles ＆ Level 2的实时编码要求,可用于MPEG-4的VLSI实现。     

一种低资源消耗的运动估计VLSI实现算法

现有的VLSI(verylarge scale integration)视频编码芯片多使用全搜索运动估计(ME)方法,且没有搜索中心偏移(CB)的并行实现方法。本文提出一种适合VLSI的H.264、AVS CB并行搜索方案,减少搜索点数量,降低逻辑资源的消耗,并且使用预测高概率区域的方法,保证ME精度。实验表明,本方法具备较好的率失真性能。在现场可编程门阵列(FPGA)平台上实现了本算法,逻辑综合的数据表明,硬件资源消耗降低了64%。本算法可应用于标清和高清电视(HDTV,hign-definition television)视频编码器。     

基于碳纳米管的电子器件

碳纳米管有着众多独特的性质 ,尤其是它的电学性质。近几年来 ,碳纳米管的研究已展示出了在纳米电子器件上的应用前景 ,即通过构建尺寸只有几十纳米甚至更小的基于碳纳米管的电子器件和连线 ,实现速度远快于而功耗远小于目前集成电路的碳纳米管集成电路。文中在讨论碳纳米管电学性质的基础上 ,主要介绍基于碳纳米管的结、场效应晶体管和单电子晶体管等最新研究和进展     

一种电迁移测试失效时间判定方法

采用铜大马士革工艺制备了用于电迁移测试的样品,对电迁移测试过程中存在的两类电阻-时间(R-t)特征曲线进行了研究.研究发现采用固定电阻变化率作为失效判定标准所得的失效时间分布曲线不能真实地反映样品的实际寿命,而采用第一次阻值跳变点对应的时间作为失效时间所得的分布曲线则更符合电迁移理论.针对两种失效判定方法所得到的不同结果进行了机理分析,结果表明,采用第一次阻值跳变点对应的时间作为失效时间分析电迁移失效更合理.     

Edge‐Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.     

Feasibility of BCB as an interlevel dielectric in integrated circuits

This paper investigates the feasibility of using an organic polymer based on benzocyclobutene as an interlevel dielectric material in very large scale integrated (VLSI) circuits. The material is a thermoset resin with attractive electrical and mechanical properties for application as an interlevel dielectric in VLSI circuits. It has a low relative dielectric constant of 2.7. The single coating planarization achieved by spin coating the material is superior to currently used materials and makes it a very attractive material for the fabrication of multilevel metal systems. The planarization properties of this material are presented and compared with those of polyimide. The patterning and dry etching of BCB to define 1 μm vias is described. As the material has limited thermal stability at temperatures greater than 350°C, compatible materials for low via resistivity have been investigated using a double level metal structure. The effect of post metal anneals on via resistivity of various via structures is presented. It is found that a low via resistivity of 3 × 10^-9 gW-cm² without any post metal anneal is obtained by using an AlCu/Pd-AlCu metallurgy.     

氮掺杂对单壁碳纳米管的非平衡电子输运特性的影响

利用结合了非平衡格林函数的第一性原理的局域密度泛函理论,研究了氮原子取代掺杂单壁碳纳米管的输运特性.计算结果表明,不同构形和不同数目的氮原子掺杂对(8,0)单壁碳管的输运性能有复杂的影响.研究发现,氮原子的掺杂提高了半导体型碳管的输运性能,电流-电压曲线呈非线性变化.对于浓度相同的氮掺杂,原胞内最近邻氮原子间距极大地影响了碳管的输运性能.因此,基于掺杂管的分子器件的设计中很有必要考虑这些因素.     

氮掺杂对单壁碳纳米管的非平衡电子输运特性的影响

利用结合了非平衡格林函数的第一性原理的局域密度泛函理论,研究了氮原子取代掺杂单壁碳纳米管的输运特性.计算结果表明,不同构形和不同数目的氮原子掺杂对(8,0)单壁碳管的输运性能有复杂的影响.研究发现,氮原子的掺杂提高了半导体型碳管的输运性能,电流-电压曲线呈非线性变化.对于浓度相同的氮掺杂,原胞内最近邻氮原子间距极大地影响了碳管的输运性能.因此,基于掺杂管的分子器件的设计中很有必要考虑这些因素.     

超大规模集成电路多孔电介质介电常数与分形维数

技术的发展要求超大规模集成电路的特征尺寸进一步降低以提高元件密度,这就需要低介电常数(k)的多孔电介质的应用.而多孔介质的输运物理性质通常与其微结构有密切关系.本文在综述多孔电介质利用分形模型分析方法的基础上,利用分形几何理论,进一步把多孔电介质介电常数(k)与反映孔微结构的分形维数联系起来,更好地适应于实际中不均一不规则的多孔电介质介电常数的分析计算.