基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

OFDM系统同步算法研究及其VLSI实现

针对正交频分复用（OFOM, Orthogonal Frequency Division Multiplex）无线传输系统,提出并设计了一种适用于802．11a标准前导序列的同步算法。首先基于接收基带数据能量判断信道空闲状态,再计算数据归一化自相关值检测帧起始位置,最后利用基带数据与参考训练序列的互相关运算检测OFDM符号的起始位置,实现同步功能。算法的硬件实现采用移位加和流水线技术来提高系统的性能与效率。实践表明,所提算法能有效地实现同步并且硬件实现复杂度低,适合于超大规模集成电路（VLSI,Very LargeScale Integration）的实现。     

Significantly Boosted Photothermoelectric Effect via Carrier Injection in Au Decorated SWCNT Films for Infrared Detection

Carbon nanotubes (CNTs) have established their promising application as infrared photodetector and the photothermoelectric (PTE) effect is demonstrated to play a critical role. While extensive studies are focused on the optoelectronic behaviors, the thermoelectric conversion involved in the PTE has been pursued to less extent probably due to the overall low thermopower under infrared (IR) illumination. Herein, to trigger a stronger PTE response, Au/CNT heterojunctions are formed by Au nanoparticles (NPs) decoration of CNT films to facilitate both light absorption and carrier transportation, so that thermoelectric property is enhanced simultaneously. Significant boost on infrared radiation energy conversion capability is therefore enabled in Au NPs decorated CNT film, delivering maximum output voltage of 26.1 mV and power of 27.3 µW, outperforming the state-of-the art photodetectors based on PTE effect. The transport mechanism is revealed via combining in situ Kelvin Probe Force Microscope mapping of the surface potential and macroscopic transport and output performances under IR illumination. Finally, the IR detection function is validated via an 8-channel IR detector prototype, presenting sensitive responsivity and long-term cyclic stability. The study thus demonstrates the PTE effect as a promising platform toward high-performance optoelectronic applications such as IR detection and solar energy harvesting.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

Process and device modeling for VISI

The appearance of Very Large Scale Integration caused a pronounced interest in concentrating on process and device modeling. The fundamental properties which represent the basis for all device modeling activities are summarized. The sensible use of physical and technological parameters is discussed and the most important physical phenomena which are required to be taken into account are scrutinized. The assumptions necessary for finding a reasonable trade-off between efficiency and effort for a model synthesis are recollected. Methods to bypass limitations induced by these assumptions are pin-pointed. Formulae that are applicable in a simple and easy way for the physical parameters of major importance are presented. The necessity of a careful parameter-selection, based on physical information, is shown. Some glimpses on the numerical solution of the semiconductor equations are given. The discretisation of the partial differential equations with finite differences is outlined. Linearisation methods and algorithms for the solution of large sparse linear systems are sketched. Results of our two dimensional MOSFET model — MINIMOS — are discussed. Much emphasis is laid on the didactic potential of such a complex high order model.     

升温速度对电场烧结NdFeB材料致密化的影响

首次将电场烧结方法引入烧结NdFeB永磁材料的制备中,通过分析压坯的温度场特征发现,在较高的预设升温速度下,压坯的实际升温过程存在延迟情况。对烧结磁体的SEM观察表明,随预设升温速度的提高,磁体的致密度逐步提高。当NdFeB合金以2000℃/s的预设升温速度在1000℃烧结8min后,磁体的微观组织明显优于传统烧结磁体。     

基于偏心Preissmann格式的高速互连线分析

 将偏心Preissmann格式应用于高速电路互连线分析,导出一种互连线离散模型.通过调整偏心参数,可以获得二阶精度的差分格式.数值仿真表明,该方法能够应用于一般互连线的瞬态分析,改善间断之后的数值扰动现象,并与特征法进行了比较,说明了方法的有效性.     

Cu含量对电场快速烧结W-Cu合金的影响

采用Gleeble—3500D热模拟机,在烧结温度为800℃,烧结时间为3 min的条件下,借助金相显微镜、扫描电镜、显微硬度测试计分析,研究了电场对烧结W-xCu(x=10%,20%,30%和40%)(质量分数)体系的影响。结果表明:本条件下,可得到密度较高、组织较均匀细小的烧结体;并且随着Cu含量的增加,烧结体致密化程度逐步提高,组织更加均匀,晶粒更加细小,平均晶粒尺寸从1.0μm降到0.3μm;但烧结体的硬度会相应降低。     

MPEG-4运动补偿的VLSI结构设计

针对MPEG．4解码中运动补偿控制复杂、数据吞吐量大、实现较困难，提出了一种适合MPEG-4的运动补偿硬件实现方案，解决了时序分配、输入输出控制等较难处理的问题。此方案已经在Xilinx ISE6．li集成开发环境下，采用了VHDL进行描述，并使用了电子设计自动化（EDA）工具进行了模拟和验证。仿真和综合结果表明，设计的运动补偿处理器逻辑功能完全正确，而且可以满足MPEG-4 Core Profiles ＆ Level 2的实时编码要求，可用于MPEG-4的VLSI实现。     

电场作用下金属元素对W-Cu合金快速烧结的影响

采用Gleeble—3500D热模拟机,在电场和大热流密度条件下,研究了金属元素(Fe、Co和Ni)对W-20%Cu合金电场快速烧结的影响。结果表明:经800℃烧结3min,可获得晶粒较细小、显微组织较均匀的烧结体;添加金属元素能有效抑制晶粒长大。质量分数为0.35%的Fe、Ni和Co分别使其平均晶粒尺寸由1.0μm减小到0.6,0.6和0.3μm。金属元素的加入,对烧结体的致密化和硬度不利。     

Solution processable PEDOT:PSS based hybrid electrodes for organic field effect transistors

We report high performance solution processed conductive inks used as contact electrodes for printed organic field effect transistors (OFETs). Poly(3,4-ethylenedioxythiophene): polystyrene sulfonate (PEDOT:PSS) electrodes show highly improved very low sheet resistance of 65.8 ± 6.5 Ω/square (Ω/□) by addition of dimethyl sulfoxide (DMSO) and post treatment with methanol (MeOH) solvent. Sheet resistance was further improved to 33.8 ± 8.6 Ω/□ by blending silver nanowire (AgNW) with DMSO doped PEDOT:PSS. Printed OFETs with state of the art diketopyrrolopyrrole-thieno[3,2-b]thiophene (DPPT-TT) semiconducting polymer were demonstrated with various solution processable conductive inks, including bare, MeOH treated PEDOT:PSS, single wall carbon nanotubes, and hybrid PEDOT:PSS-AgNW, as the source and drain (S/D) electrode by spray printing using a metal shadow mask. The highest field effect mobility, 0.49 ± 0.03 cm² V⁻¹ s⁻¹ for DPPT-TT OFETs, was obtained using blended AgNW with DMSO doped PEDOT:PSS S/D electrode.     

锯齿型单壁碳纳米管的光电性质

应用基于广义梯度近似的密度泛函理论中的简化广义梯度近似方法(PBE)对(7,0)至(18,0)锯齿型单壁碳纳米管在极化与非极化条件下从紫外波段到近红外波段的光电性质分别做了理论计算,得到了锯齿型碳纳米管的各光学常数峰值和各光学常数峰值所对应的波长与其手性参数n之间的对应关系和变化趋势。结果表明:除反射率和损耗外的各光学常数的峰值是随着n的增大而减小的;除反射率峰值对应波长外,其它光学常数的峰值对应的波长值随着n的增大逐渐趋于一个恒定值。     

大规模集成电路浮栅ROM器件总剂量辐射效应

提出了一种大规模集成电路总剂量效应测试方法:在监测器件和电路功能参数的同时,监测器件功耗电流的变化情况,分析数据错误和器件功耗电流与辐射总剂量的关系.根据该方法利用60Co γ射线进行了浮栅ROM集成电路(AT29C256)总剂量辐照实验,研究了功耗电流和出错数量在不同γ射线剂量率辐照下的总剂量效应,以及参数失效与功能失效时间随辐射剂量率的变化关系,并利用外推实验技术预估了电路在空间低剂量率环境下的失效时间.     

大规模集成电路浮栅ROM器件总剂量辐射效应

提出了一种大规模集成电路总剂量效应测试方法:在监测器件和电路功能参数的同时,监测器件功耗电流的变化情况,分析数据错误和器件功耗电流与辐射总剂量的关系.根据该方法利用60Co γ射线进行了浮栅ROM集成电路(AT29C256)总剂量辐照实验,研究了功耗电流和出错数量在不同γ射线剂量率辐照下的总剂量效应,以及参数失效与功能失效时间随辐射剂量率的变化关系,并利用外推实验技术预估了电路在空间低剂量率环境下的失效时间.     

半导体型单壁碳纳米管的电子输运特性

采用基于密度泛函理论的非平衡格林函数法(Non-equilibrium Green functions,NEGF),对耦合于两个面心立方间的Al(111)电极间的(8,0)碳纳米管(Carbon nanotube,CNT)传输特性进行了计算。结果表明,在小偏压下(-40～40 mV),碳纳米管伏安特性与孤立碳纳米管的接近为零不同,而是接近为线性,这是耦合导致碳纳米管能级移动的结果。     

预设升温速度对W-Cu合金性能的影响

采用Gleeble—3500D热模拟机,通过对烧结体密度、显微结构以及硬度的分析,研究了电场作用下预设升温速度对W-20Cu体系快速烧结的影响。结果表明:W-20Cu复合粉在800℃、较短时间(3min)内进行快速烧结可得到烧结性能良好、平均晶粒尺寸约0.4μm的W-Cu合金;并且随着预设升温速度的提高,电场的作用愈强,压坯所获得的热流密度愈大,这有利于烧结体的致密化;同时,预设升温速度的提高,合金的硬度呈递增趋势。     

全透明低回滞s-SWCNT/AgNW薄膜晶体管的可控制备

利用高纯度、高均一性的半导体型单壁碳纳米管(s-SWCNT)网络薄膜作为薄膜晶体管的沟道材料,以高透明度、低薄膜电阻的银纳米线(Ag NW)网络薄膜作为源、漏电极,在玻璃基底上制备了大面积、高透明度的碳纳米管薄膜晶体管阵列,并使用聚甲基丙烯酸甲酯(PMMA)薄膜在器件表面通过干法封装获得了较低回滞的电子器件,得到了整体透明度达到82%以上的器件。提出的器件制备方法不仅制备材料易得,不需要高温过程,而且能够实现器件的大面积制备,对碳纳米管薄膜晶体管的全透明柔性化进程具有推进作用。     

一种低资源消耗的运动估计VLSI实现算法

现有的VLSI(verylarge scale integration)视频编码芯片多使用全搜索运动估计(ME)方法,且没有搜索中心偏移(CB)的并行实现方法。本文提出一种适合VLSI的H.264、AVS CB并行搜索方案,减少搜索点数量,降低逻辑资源的消耗,并且使用预测高概率区域的方法,保证ME精度。实验表明,本方法具备较好的率失真性能。在现场可编程门阵列(FPGA)平台上实现了本算法,逻辑综合的数据表明,硬件资源消耗降低了64%。本算法可应用于标清和高清电视(HDTV,hign-definition television)视频编码器。     

一种电迁移测试失效时间判定方法

采用铜大马士革工艺制备了用于电迁移测试的样品,对电迁移测试过程中存在的两类电阻-时间(R-t)特征曲线进行了研究.研究发现采用固定电阻变化率作为失效判定标准所得的失效时间分布曲线不能真实地反映样品的实际寿命,而采用第一次阻值跳变点对应的时间作为失效时间所得的分布曲线则更符合电迁移理论.针对两种失效判定方法所得到的不同结果进行了机理分析,结果表明,采用第一次阻值跳变点对应的时间作为失效时间分析电迁移失效更合理.     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.